UJA1078ATW Datasheet, PDF (15/54 Pages) NXP Semiconductors – High-speed CAN/dual LIN core system basis chip

NXP Semiconductors
UJA1078A
High-speed CAN/dual LIN core system basis chip
Table 6. Int_Control register …continued
Bit Symbol Access Power-on Description
default
3
STBCC R/W 0
CAN standby control
0: When the SBC is in Normal mode (MC = 1x):
CAN is in Active mode. The wake-up flag (visible on RXDC) is cleared
regardless of V2 output voltage.
When the SBC is in Standby/Sleep mode (MC = 0x):
CAN is in Off mode. Bus wake-up detection is disabled. CAN wake-up
interrupts cannot be requested.
1: CAN is in Lowpower mode with bus wake-up detection enabled,
regardless of the SBC mode (MC = xx). CAN wake-up interrupts can be
requested.
2
RTHC
R/W 0
reset threshold control
1
WSE1
R/W 0
0: The reset threshold is set to the 90 % V1 undervoltage detection voltage
(V_uvd; see Table 10)
1: The reset threshold is set to the 70 % V1 undervoltage detection voltage
(V_uvd; see Table 10)
WAKE1 sample enable
0: sampling continuously
1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled
by WBC)
0
WSE2
R/W 0
WAKE2 sample enable
0: sampling continuously
1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled
by WBC)
UJA1078A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 28 January 2011
© NXP B.V. 2011. All rights reserved.
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