TDA8310A Datasheet, PDF (16/24 Pages) NXP Semiconductors – PAL/NTSC colour processor for PIP applications

Philips Semiconductors
PAL/NTSC colour processor
for PIP applications
Product specification
TDA8310A
11. At a chrominance input voltage of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude
300 mV (p-p)) as given in Characteristics first parameter of Section “Chrominance input (pin 16)” the dynamic range
of the ACC is +6 and −20 dB.
12. All frequency variations are referenced to 3.58/4.43 MHz carrier frequency. All oscillator specifications are measured
with the Philips crystal series 9922 520. If the spurious response of the 4.43 MHz crystal is lower than −3 dB with
respect to the fundamental frequency for a damping resistance of 1 kΩ, oscillation at the fundamental frequency is
guaranteed. The spurious response of the 3.58 MHz crystal must be lower than −3 dB with respect to the
fundamental frequency for a damping resistance of 1.5 kΩ. The catching and detuning range are measured for
nominal crystal parameters. These are:
a) Load resonance frequency f₀ (C_L = 20 pF) = 4.433619 or 3.579545 MHz
b) Motional capacitance C_M = 20.6 fF (4.43 MHz crystal) or 14.7 fF (3.58 MHz crystal)
c) Parallel capacitance C₀ = 5.5 pF (4.43 MHz crystal) or 4.5 pF (3.58 MHz crystal).
The actual load capacitance in the application should be C_L = 18 pF to account for parasitic capacitances on and
off chip.
The free-running frequency of the oscillator can be checked by the HUE control pin to the positive supply rail. In that
condition the colour killer is not active so that the frequency offset is visible on the screen. When two or more crystals
are connected to the IC the circuit must be forced to one of the crystals during this test to prevent the oscillator
continuously switching between the various frequencies.
13. The reference signal for the TDA8395 is available only when the crystal oscillator is operating at a frequency of
4.43 MHz. When a SECAM signal is identified this signal is only available during the vertical retrace period thus
avoiding crosstalk with the incoming SECAM signal during scan.
14. The identified colour standard can be read from the IC in two ways:
a) From the voltage level of pin 4. The voltage during the demodulation of the various standards is given in the last
three parameters of this section.
b) From the pins 23 to 26 when pin 27 is in the ‘read’ mode.
When pin 27 is in the ‘write’ mode the colour decoder can be forced to one of the colour standards. The levels for the
various standards are given in Tables 1, 2 and 3.
15. The control possibilities of the RGB switch via pins 13 and 52 are shown in Table 4.
16. To obtain a simple interface between the TDA8310A and the PIP processor the sandcastle output has been designed
such that the output is pulled down during scan and pulled up during the burst key pulse. During blanking the output
is high-ohmic and therefore the output voltage is determined by the load.
17. The output of pin 4 is designed similar to the sandcastle output. The output is pulled down during PAL and pulled up
during SECAM. During NTSC the pin is floating so that the output level is determined by the load.
18. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is
switched depending on the input signal condition. Therefore the circuit contains a noise detector and the time
constant is switched to ‘slow’ when excessive noise is present in the signal. This occurs when the internal video
signal is selected or for an external CVBS signal when the chrominance input (pin 16) is left open-circuit. The time
constant is always ‘fast’ when the chrominance input pin is connected to ground and the input is switched to the Y/C
mode. In the ‘fast’ mode during the vertical retrace time the phase detector current is increased 50% so that phase
errors due to head-switching of the VCR are corrected as soon as possible.
During weak signal conditions (noise detector active) the phase detector is gated and the width of the gate pulse has
a value of 5.7 µs so that the effect of the noise is reduced to a minimum.
The output current of the phase detector for the various conditions is shown in Table 5.
19. This value indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass filter.
The bandwidth of the demodulator low-pass filter is approximately 1 MHz.
1996 Jan 25
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