80C552 Datasheet, PDF (13/23 Pages) NXP Semiconductors – Single-chip 8-bit microcontroller

Philips Semiconductors
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
Product data
80C552/83C552
AC ELECTRICAL CHARACTERISTICS^{1, 2}
16 MHz version
16 MHz CLOCK
VARIABLE CLOCK
SYMBOL FIGURE
PARAMETER
MIN
MAX
MIN
MAX
1/t_CLCL
2
Oscillator frequency
t_LHLL
2
ALE pulse width
85
t_AVLL
2
Address valid to ALE low
8
t_LLAX
2
Address hold after ALE low
28
t_LLIV
2
ALE low to valid instruction in
t_LLPL
2
ALE low to PSEN low
23
t_PLPH
2
PSEN pulse width
143
t_PLIV
2
PSEN low to valid instruction in
t_PXIX
2
Input instruction hold after PSEN
0
t_PXIZ
2
Input instruction float after PSEN
t_AVIV
2
Address to valid instruction in
t_PLAZ
2
PSEN low to address float
Data Memory
3.5
16
2t_CLCL–40
t_CLCL–55
t_CLCL–35
150
4t_CLCL–100
t_CLCL–40
3t_CLCL–45
83
3t_CLCL–105
0
38
t_CLCL–25
208
5t_CLCL–105
10
10
t_RLRH
3
RD pulse width
275
6t_CLCL–100
t_WLWH
4
WR pulse width
275
6t_CLCL–100
t_RLDV
3
RD low to valid data in
148
5t_CLCL–165
t_RHDX
3
Data hold after RD
0
0
t_RHDZ
3
Data float after RD
55
2t_CLCL–70
t_LLDV
3
ALE low to valid data in
350
8t_CLCL–150
t_AVDV
3
Address to valid data in
398
9t_CLCL–165
t_LLWL
3, 4 ALE low to RD or WR low
138
238
3t_CLCL–50 3t_CLCL+50
t_AVWL
3, 4 Address valid to WR low or RD low
120
4t_CLCL–130
t_QVWX
4
Data valid to WR transition
3
t_CLCL–60
t_DW
4
Data before WR
288
7t_CLCL–150
t_WHQX
4
Data hold after WR
13
t_CLCL–50
t_RLAZ
3
RD low to address float
0
0
t_WHLH
3, 4 RD or WR high to ALE high
23
103
t_CLCL–40
t_CLCL+40
External Clock
t_CHCX
5
High time⁴
20
20
t_CLCX
5
Low time⁴
20
20
t_CLCH
5
Rise time⁴
20
20
t_CHCL
5
Fall time⁴
20
20
Serial Timing – Shift Register Mode⁴ (Test Conditions: T_amb = 0 °C to +70 °C; V_SS = 0 V; Load Capacitance = 80 pF)
t_XLXL
6
Serial port clock cycle time
0.75
12t_CLCL
t_QVXH
6
Output data setup to clock rising edge
492
10t_CLCL–133
t_XHQX
6
Output data hold after clock rising edge
8
2t_CLCL–117
t_XHDX
6
Input data hold after clock rising edge
0
0
t_XHDV
6
Clock rising edge to input data valid
492
10t_CLCL–133
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. t_CLCL = 1/f_OSC = one oscillator clock period.
t_CLCL = 83.3ns at f_OSC = 12 MHz.
t_CLCL = 62.5ns at f_OSC = 16 MHz.
4. These values are characterized but not 100% production tested.
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
2002 Sep 03
13