80C552 Datasheet, PDF (11/23 Pages) NXP Semiconductors – Single-chip 8-bit microcontroller

Philips Semiconductors
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
Product data
80C552/83C552
DC ELECTRICAL CHARACTERISTICS (Continued)
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
Analog Inputs
AI_DD
Analog supply current: operating: (16 MHz)
Analog supply current: operating: (24 MHz)
Port 5 = 0 to AV_DD
Port 5 = 0 to AV_DD
1.2
mA
1.0
mA
AI_ID
Idle mode:
P83(0)C552EBx
P83(0)C552EFx
P83(0)C552EHx
P83(0)C552IBx
P83(0)C552IFx
50
µA
50
µA
100
µA
50
µA
50
µA
AI_PD
Power-down mode:
P83(0)C552xBx
P83(0)C552xFx
P83(0)C552xHx
2 V < AV_PD < AV_DD
max
50
µA
50
µA
100
µA
AV_IN
Analog input voltage
AV_SS–0.2 AV_DD+0.2
V
AV_REF
Reference voltage:
AV_REF–
AV_REF+
AV_SS–0.2
V
AV_DD+0.2
V
R_REF
Resistance between AV_REF+ and AV_REF–
10
50
kΩ
C_IA
Analog input capacitance
15
pF
t_ADS
Sampling time
8t_CY
µs
t_ADC
Conversion time (including sampling time)
50t_CY
µs
DL_e
Differential non-linearity^{10, 11, 12}
±1
LSB
IL_e
Integral non-linearity^{10, 13}
±2
LSB
OS_e
G_e
Offset error^{10, 14}
Gain error^{10, 15}
±2
LSB
±0.4
%
A_e
Absolute voltage error^{10, 16}
±3
LSB
M_CTC
Channel to channel matching
±1
LSB
C_t
Crosstalk between inputs of port 5¹⁷
0–100kHz
–60
dB
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 10 through 15 for I_DD test conditions.
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t_r = t_f = 10 ns; V_IL = V_SS + 0.5 V;
V_IH = V_DD – 0.5 V; XTAL2 not connected; EA = RST = Port 0 = EW = V_DD; STADC = V_SS.
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t_r = t_f = 10 ns; V_IL = V_SS + 0.5 V;
V_IH = V_DD – 0.5 V; XTAL2 not connected; Port 0 = EW = V_DD; EA = RST = STADC = V_SS.
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = V_DD;
EA = RST = STADC = XTAL1 = V_SS.
5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I²C specification, so an input voltage below 1.5 V will be recognized as a
logic 0 while an input voltage above 3.0 V will be recognized as a logic 1.
6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when V_IN is approximately 2 V.
7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V_OLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I_OL can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
8. Capacitive loading on ports 0 and 2 may cause the V_OH on ALE and PSEN to momentarily fall below the 0.9 V_DD specification when the
address bits are stabilizing.
9. The following condition must not be exceeded: V_DD – 0.2 V < AV_DD < V_DD + 0.2 V.
10. Conditions: AV_REF– = 0 V; AV_DD = 5.0 V, AV_REF+ (80C552, 83C552) = 5.12 V. ADC is monotonic with no missing codes. Measurement by
continuous conversion of AV_IN = –20 mV to 5.12 V in steps of 0.5 mV.
11. The differential non-linearity (DL_e) is the difference between the actual step width and the ideal step width. (See Figure 1.)
12. The ADC is monotonic; there are no missing codes.
13. The integral non-linearity (IL_e) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset error. (See Figure 1.)
2002 Sep 03
11