74HC4510 Datasheet, PDF (11/12 Pages) NXP Semiconductors – BCD up/down counter

Philips Semiconductors
BCD up/down counter
APPLICATION INFORMATION
Product specification
74HC/HCT4510
Terminal count (TC) lines at the 2nd, 3rd, etc. stages may have a negative-going
glitch pulse resulting from differential delays of different 4510s. These
negative-going glitches do not affect proper 4510 operation. However, if the
terminal count signals are used to trigger other edge sensitive logic devices, such
as flip-flops or counters, the terminal count signals should be gated with the clock
signal using a 2-input OR gate such as HC/HCT32.
Fig.12 Cascading counter packages (parallel clocking).
Ripple clocking mode: the UP/DN control can be changed at any count. The only
restriction on changing the UP/DN control is that the clock input to the first counting
stage must be “HIGH”. For cascading counters operating in a fixed up-count or
down-count mode, the OR gates are not required between stages and TC is
connected directly to the CP input of the next stage with CE grounded.
Fig.13 Cascading counter packages (ripple clocking).
December 1990
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