74HC4510 Datasheet, PDF (10/12 Pages) NXP Semiconductors – BCD up/down counter

Philips Semiconductors
BCD up/down counter
Product specification
74HC/HCT4510
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.9 Waveforms showing the preset enable
pulse width, preset enable to output
delays and output transition times.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.10 Waveforms showing the master reset pulse,
master reset to terminal count and Q_n delay
and master reset to clock removal time.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.11 Waveforms showing the data set-up and
hold times to parallel load (PL).
December 1990
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