TDA8763 Datasheet, PDF (10/24 Pages) NXP Semiconductors – 10-bit high-speed low-power ADC with internal reference regulator

Philips Semiconductors
10-bit high-speed low-power ADC with
internal reference regulator
Product specification
TDA8763
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
TWO-TONE; note 8
TTIR
two-tone intermodulation
rejection
f_clk = 40 MHz
−
−69 −
dB
BIT ERROR RATE
BER
bit error rate
DIFFERENTIAL GAIN; note 9
G_diff
differential gain
f_clk = 50 MHz;
−
f_i = 4.43 MHz;
V_I = ±16 LSB at code 512
f_clk = 40 MHz;
−
PAL modulated ramp
10^−13 −
0.8
−
times/
sample
%
DIFFERENTIAL PHASE; note 9
ϕ_diff
differential phase
f_clk = 40 MHz;
−
0.4
−
deg
PAL modulated ramp
Timing (f_clk = 40 MHz; C_L = 15 pF); see Fig.4; note 10
t_ds
sampling delay time
t_h
output hold time
t_d
output delay time
V_CCO = 4.75 V
V_CCO = 3.15 V
C_L
digital output load capacitance
−
3
−
ns
4
−
−
ns
−
10
13
ns
−
12
15
ns
−
−
15
pF
3-state output delay times; see Fig.5
t_dZH
enable HIGH
t_dZL
enable LOW
t_dHZ
disable HIGH
t_dLZ
disable LOW
−
5.5
8.5
ns
−
12
15
ns
−
19
24
ns
−
12
15
ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.
2. Analog input voltages producing code 0 up to and including code 1023:
a) V_offset(B) (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00
and the reference voltage BOTTOM (V_RB) at T_amb = 25 °C.
b) V_offset(T) (voltage offset TOP) is the difference between reference voltage TOP (V_RT) and the analog input which
produces data outputs equal to code 1023 at T_amb = 25 °C.
1999 Jan 06
10