74HC_HCT166_15 Datasheet, PDF (10/21 Pages) NXP Semiconductors – 8-bit parallel-in/serial out shift register

NXP Semiconductors
74HC166; 74HCT166
8-bit parallel-in/serial out shift register
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); t_r = t_f = 6 ns: C_L = 50 pF unless otherwise specified; for test circuit, see Figure 10
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max
Min
Max
t_h
hold time
Dn, CE to CP; see Figure 9
V_CC = 2.0 V
2 8
-
2
-
2
- ns
V_CC = 4.5 V
2 3
-
2
-
2
- ns
V_CC = 6.0 V
2 2
-
2
-
2
- ns
PE to CP; see Figure 9
V_CC = 2.0 V
0 28 -
0
-
0
- ns
V_CC = 4.5 V
0 10 -
0
-
0
- ns
V_CC = 6.0 V
0 8 -
0
-
0
- ns
f_max
maximum CP input; see Figure 7
frequency
V_CC = 2.0 V
6 19 -
4.8
-
4
- MHz
V_CC = 4.5 V
30 57 -
24
-
20
- MHz
V_CC = 5.0 V; C_L = 15 pF
- 63 -
-
-
-
- MHz
V_CC = 6.0 V
35 68 -
28
-
24
- MHz
C_PD
power
per package;
dissipation V_I = GND to V_CC
capacitance
[3] _{- 41 -}
-
-
-
- pF
74HCT166
t_pd
propagation CP to Q7; see Figure 7
[1]
delay
V_CC = 4.5 V
- 23 40
-
50
-
60 ns
V_CC = 5.0 V; C_L = 15 pF
- 20 -
-
-
-
- ns
MR to Q7; see Figure 8
V_CC = 4.5 V
- 22 40
-
50
-
60 ns
V_CC = 5.0 V; C_L = 15 pF
- 19 -
-
-
-
- ns
t_t
transition
output; see Figure 7
time
V_CC = 4.5 V
[2]
- 7 15
-
19
-
22 ns
t_W
pulse width CP input HIGH or LOW;
see Figure 7
V_CC = 4.5 V
20 9 -
25
-
30
- ns
MR input LOW; see Figure 8
V_CC = 4.5 V
25 11 -
31
-
38
- ns
t_rec
recovery time MR to CP; see Figure 8
V_CC = 4.5 V
0 7
-
0
-
0
- ns
t_su
set-up time Dn, CE to CP; see Figure 9
V_CC = 4.5 V
16 8 -
20
-
24
- ns
PE to CP; see Figure 9
V_CC = 4.5 V
30 15 -
38
-
45
- ns
t_h
hold time
Dn, CE to CP; see Figure 9
V_CC = 4.5 V
0 3
-
0
-
0
- ns
PE to CP; see Figure 9
V_CC = 4.5 V
0 13 -
0
-
0
- ns
74HC_HCT166
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 11 September 2013
© NXP B.V. 2013. All rights reserved.
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