74HC4094 Datasheet, PDF (10/10 Pages) NXP Semiconductors – 8-stage shift-and-store bus register

Philips Semiconductors
8-stage shift-and-store bus register
AC WAVEFORMS
Product specification
74HC/HCT4094
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.7
Waveforms showing the clock (CP) to
output (QP_n, QS₁, QS₂) propagation
delays, the clock pulse width and the
maximum clock frequency.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.8
Waveforms showing the strobe (STR) to
output (QP_n) propagation delays and the
strobe pulse width and the clock set-up and
hold times for the strobe input.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.9 Waveforms showing the 3-state enable and
disable times for input OE.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3 V; V_I = GND to 3 V.
Fig.10 Waveforms showing the data set-up and
hold times for the data input (D).
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
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