GTL2007 Datasheet, PDF (1/19 Pages) NXP Semiconductors – 13-bit GTL to LVTTL translator with power good control

GTL2007
13-bit GTL to LVTTL translator with power good control
Rev. 01 — 2 June 2005
Product data sheet
1. General description
The GTL2007 is a customized translator between dual Xeon processors, Platform Health
Management, South Bridge and Power Supply LVTTL and GTL signals.
The GTL2007 is derived from the GTL2006 with an enable function added that disables
the error output to the monitoring agent for platforms that monitor the individual error
conditions from each processor. This enable function can be used so that false error
conditions are not passed to the monitoring agent when the system is unexpectedly
powered down. This unexpected power-down could be from a power supply overload, a
CPU thermal trip, or some other event of which the monitoring agent is unaware.
A typical implementation would be to connect each enable line to the system power good
signal or the individual enables to the VRD power good for each processor.
The Nocona and Dempsey/Blackford Xeon processors specify a V_TT of 1.2 V and 1.1 V,
as well as a nominal V_ref of 0.76 V and 0.73 V respectively. To allow for future voltage level
changes that may extend V_ref to 0.63 of V_TT (minimum of 0.693 V with V_TT of 1.1 V) the
GTL2009 allows a minimum V_ref of 0.66 V. Characterization results show that there is little
DC or AC performance variation between these levels.
The GTL2007 is the companion chip to the GTL2009 3-bit GTL Front-Side Bus frequency
comparator that is used in dual-processor Xeon applications.
2. Features
s Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver
s 3.0 V to 3.6 V operation
s LVTTL I/O not 5 V tolerant
s Series termination on the LVTTL outputs of 30 Ω
s ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
s Latch-up testing is done to JEDEC Standard JESD78 which exceeds 500 mA
s Package offered: TSSOP28