BUK563-80B Datasheet, PDF (1/7 Pages) NXP Semiconductors – PowerMOS Transistor Logic level FET

Philips Semiconductors
PowerMOS Transistor
Logic level FET
Product specification
BUK563-80B
GENERAL DESCRIPTION
N-channel enhancement mode
logic level field-effect power
transistor in a plastic envelope.
The device is intended for use in
Switched Mode Power Supplies
(SMPS), motor control, welding,
DC/DC and AC/DC converters, and
in automotive and general purpose
switching applications.
QUICK REFERENCE DATA
SYMBOL PARAMETER
V_DS
I_D
P_tot
T_j
R_DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V_GS = 5 V
MAX.
80
16
75
175
0.155
UNIT
V
A
W
˚C
Ω
PINNING - SOT404
PIN
DESCRIPTION
1 gate
2 drain
3 source
mb drain
PIN CONFIGURATION
mb
2
13
SYMBOL
d
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
V_DS
V_DGR
±V_GS
I_D
I_D
I_DM
P_tot
T_stg
T_j
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage temperature
Junction temperature
-
R_GS = 20 kΩ
-
T_mb = 25 ˚C
T_mb = 100 ˚C
T_mb = 25 ˚C
T_mb = 25 ˚C
-
-
THERMAL RESISTANCES
SYMBOL
R_{th j-mb}
R_{th j-a}
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
minimum footprint, FR4 board
(see Fig. 18)
MIN.
-
-
-
-
-
-
-
- 55
-
MAX.
80
80
15
16
11
64
75
175
175
UNIT
V
V
V
A
A
A
W
˚C
˚C
TYP.
-
50
MAX.
1.2
-
UNIT
K/W
K/W
February 1996
1
Rev 1.000