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BUK553-48C Datasheet, PDF (1/9 Pages) NXP Semiconductors – PowerMOS transistor Voltage clamped logic level FET
Philips Semiconductors
PowerMOS transistor
Voltage clamped logic level FET
Product specification
BUK553-48C
GENERAL DESCRIPTION
Protected N-channel enhancement
mode logic level field-effect power
transistor in a plastic envelope.
The device is intended for use in
automotive applications. It has
built-in zener diodes providing active
drain voltage clamping.
PINNING - TO220AB
PIN
DESCRIPTION
1 gate
2 drain
3 source
tab drain
QUICK REFERENCE DATA
SYMBOL PARAMETER
V(CL)DSR
ID
Ptot
Tj
WDSRR
RDS(ON)
Drain-source clamp voltage
Drain current (DC)
Total power dissipation
Junction temperature
Repetitive clamped turn off
energy; Tj = 150˚C
Drain-source on-state
resistance; VGS = 5 V
MIN. TYP. MAX. UNIT
40 48 58 V
21 A
75 W
175 ˚C
50 mJ
85 mΩ
PIN CONFIGURATION
SYMBOL
d
tab
1 23
g
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDG
±VGS
ID
ID
IDM
Ptot
Tstg
Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak
value)
Total power dissipation
Storage temperature
Junction Temperature
continuous
continuous
-
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
-
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb
Rth j-a
Thermal resistance junction to
heatsink
Thermal resistance junction to
ambient
CONDITIONS
with heatsink compound
MIN.
-
-
-
-
-
-
-
- 55
- 55
MAX.
30
30
15
21
15
84
75
175
175
UNIT
V
V
V
A
A
A
W
˚C
˚C
MIN. TYP. MAX. UNIT
-
-
2 K/W
-
60
- K/W
August 1994
1
Rev 1.000