BUK113-50DL Datasheet, PDF (1/6 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Objective specification
BUK113-50DL
DESCRIPTION
Monolithic overload protected logic
level power MOSFET in a surface
mount plastic envelope, intended as
a general purpose switch for
automotive systems and other
applications.
APPLICATIONS
General controller for driving
lamps
small motors
solenoids
QUICK REFERENCE DATA
SYMBOL PARAMETER
V_DS
Continuous drain source voltage
I_D
Drain current limiting
P_D
Total power dissipation
T_j
R_DS(ON)
Continuous junction temperature
Drain-source on-state resistance
MIN. MAX. UNIT
-
50
V
4
8
A
-
4
W
- 150 ˚C
- 200 mΩ
FEATURES
Vertical power DMOS output
stage
Overload protected up to
125˚C ambient
Overload protection by current
limiting and overtemperature
sensing
Latched overload protection
reset by input
5 V logic compatible input level
Control of power MOSFET
and supply of overload
protection circuits
derived from input
Low operating input current
permits direct drive by
micro-controller
ESD protection on all pins
Overvoltage clamping for turn
off of inductive loads
FUNCTIONAL BLOCK DIAGRAM
INPUT
O/V
CLAMP
RIG
LOGIC AND
PROTECTION
DRAIN
POWER
MOSFET
SOURCE
PINNING - SOT223
PIN
DESCRIPTION
1 input
2 drain
3 source
4 drain (tab)
Fig.1. Elements of the TOPFET.
PIN CONFIGURATION
SYMBOL
4
D
TOPFET
I
P
1
2
3
S
January 1996
1
Rev 1.000