74F385 Datasheet, PDF (1/6 Pages) NXP Semiconductors – Quad serial adder/subtractor

Philips Semiconductors
Quad serial adder/subtractor
Product specification
74F385
FEATURES
• Four independent adders/subtractors
• Two’s complement arithmetic
• Synchronous operation
• Common Clear and Clock
• 74F385 is designed for use with serial multipliers in implementing
digital filters and butterfly networks in fast Fourier transforms
DESCRIPTION
The 74F385 contains four independent adder/subtractor elements
with common Clock and Master Reset. Each adder/subtractor
contains a sum flop-flop and a carry flip-flop for synchronous
operations. Flip-flop state changes occur on the rising edge of the
Clock Pulse (CP) input signal. The Select (S) input should be Low
for the Add (A plus B) mode and High for the Subtract (A minus B)
mode. A Low signal on the asynchronous Master Reset (MR) input
clears the sum flip-flop and resets the Carry flip-flop to zero in the
Add mode or presets it to one in the Subtract mode.
PIN CONFIGURATION
CP 1
F0 2
S0 3
B0 4
A0 5
A1 6
B1 7
S1 8
F1 9
GND 10
TYPE
74F385
TYPICAL f_MAX
140 MHz
20 _VCC
19 _F3
18 _S3
17 _B3
16 _A3
15 A2
14 B2
13 S2
12 F2
11 MR
SF00928
TYPICAL SUPPLY
CURRENT (TOTAL)
55mA
ORDERING INFORMATION
DESCRIPTION
20-pin plastic DIP
COMMERCIAL RANGE
V_CC = 5V ±10%, T_amb = 0°C to +70°C
N74F385N
20-pin plastic SO
N74F385D
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
A0 – A3
A operand inputs
B0 – B3
B operand inputs
S0 – S3
Function select inputs
CP
Clock pulse input (active rising edge)
MR
Asynchronous Master Reset input (active Low)
F0–F3
Sum or difference outputs
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
74F (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
1989 Sep 20
1
853–0868 97678