PI7C8140AMAE Datasheet, PDF (59/82 Pages) Pericom Semiconductor Corporation – 2-Port PCI-to-PCI Bridge

PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
13 CONFIGURATION REGISTERS
PCI configuration defines a 64-byte DWORD to define various attributes of PI7C8140A as shown
below.
13.1 REGISTER TYPES
REGISTER TYPE
RO
RW
RWC
RWR
RWS
DEFINITION
Read Only
Read / Write
Read / Write 1 to Clear
Read / Write 1 to Reset (for about 20 clocks)
Read / Write 1 to Set
13.2 CONFIGURATION REGISTER
31 – 24
23 – 16
15 – 8
7–0
Device ID
Vendor ID
Primary Status
Command
Class Code
Revision ID
Reserved
Header Type
Primary Latency
Timer
Cache Line Size
Reserved
Secondary Latency Subordinate Bus
Secondary Bus
Primary Bus
Timer
Number
Number
Number
Secondary Status
I/O Limit Address I/O Base Address
Memory Limit Address
Memory Base Address
Prefetchable Memory Limit Address
Prefetchable Memory Base Address
Prefetchable Memory Base Address Upper 32-bit
Prefetchable Memory Limit Address Upper 32-bit
I/O Limit Address Upper 16-bit
I/O Base Address Upper 16-bit
Reserved
Capability Pointer
Reserved
Bridge Control
Interrupt Pin
Interrupt Line
Subsystem ID
Subsystem Vendor ID
Arbiter Control
Diagnostic / Chip Control
Reserved
Extended Chip Control
Secondary Bus
Arbiter Preemption
Reserved
Control
Reserved
Reserved
P_SERR# Event
Disable
Reserved
P_SERR# Status
Secondary Clock Control
CLKRUN
Reserved
Reserved
Reserved
Port Option
Reserved
Power Management Capabilities
Next Item Pointer
Capability ID
Reserved
Power Management Data
Secondary Master Timeout Counter
Primary Master Timeout Counter
Reserved
Reserved
HSCSR
Next Item Pointer
Capability ID
Reserved
Hot Swap Switch
Reserved
DWORD ADDRESS
00h
04h
08h
0Ch
10h – 14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
48h
4Ch
50h – 60h
64h
68h
6Ch
70h
74h
78h – 7Ch
80h
84h
88h
8Ch
90h
94h
98h – BFh
07-0067
Page 59 of 82
March 20, 2007 – Revision 1.01