PI7C8140AMAE Datasheet, PDF (45/82 Pages) Pericom Semiconductor Corporation – 2-Port PCI-to-PCI Bridge

PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
For upstream transactions, when the parity error is being passed back from the target bus and the parity
error condition was not originally detected on the initiator bus, the following events occur:
Bridge asserts S_PERR# two cycles after the data transfer, if the following are both true:
The parity error response bit is set in the command register of the primary interface.
The parity error response bit is set in the bridge control register of the secondary interface.
Bridge completes the transaction normally.
5.2.4 POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when the bridge responds as a target, it detects a data
parity error on the initiator (primary) bus and the following events occur:
Bridge asserts P_PERR# two cycles after the data transfer, if the parity error response bit is set in
the command register of primary interface.
Bridge sets the parity error detected bit in the status register of the primary interface.
Bridge captures and forwards the bad parity condition to the secondary bus.
Bridge completes the transaction normally.
Similarly, during upstream posted write transactions, when the bridge responds as a target, it detects a
data parity error on the initiator (secondary) bus, the following events occur:
Bridge asserts S_PERR# two cycles after the data transfer, if the parity error response bit is set in
the bridge control register of the secondary interface.
Bridge sets the parity error detected bit in the status register of the secondary interface.
Bridge captures and forwards the bad parity condition to the primary bus.
Bridge completes the transaction normally.
During downstream write transactions, when a data parity error is reported on the target (secondary) bus
by the target’s assertion of S_PERR#, the following events occur:
Bridge sets the data parity detected bit in the status register of secondary interface, if the parity
error response bit is set in the bridge control register of the secondary interface.
Bridge asserts P_SERR# and sets the signaled system error bit in the status register, if all the
following conditions are met:
The SERR# enable bit is set in the command register.
The posted write parity error bit of P_SERR# event disable register is not set.
The parity error response bit is set in the bridge control register of the secondary interface.
The parity error response bit is set in the command register of the primary interface.
Bridge has not detected the parity error on the primary (initiator) bus which the parity
error is not forwarded from the primary bus to the secondary bus.
During upstream write transactions, when a data parity error is reported on the target (primary) bus by
the target’s assertion of P_PERR#, the following events occur:
Bridge sets the data parity detected bit in the status register, if the parity error response bit is set in
the command register of the primary interface.
Bridge asserts P_SERR# and sets the signaled system error bit in the status register, if all the
following conditions are met:
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Page 45 of 82
March 20, 2007 – Revision 1.01