PI7C8140AMAE Datasheet, PDF (44/82 Pages) Pericom Semiconductor Corporation – 2-Port PCI-to-PCI Bridge

PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
For downstream transactions, when the bridge is delivering data to the target on the secondary bus and
S_PERR# is asserted by the target, the following events occur:
The bridge sets the secondary interface data parity detected bit in the secondary status register, if
the secondary parity error response bit is set in the bridge control register.
The bridge captures the parity error condition to forward it back to the initiator on the primary bus.
Similarly, for upstream transactions, when the bridge is delivering data to the target on the primary bus
and P_PERR# is asserted by the target, the following events occur:
The bridge sets the primary interface data-parity-detected bit in the status register, if the primary
parity-error-response bit is set in the command register.
The bridge captures the parity error condition to forward it back to the initiator on the secondary
bus.
A delayed write transaction is completed on the initiator bus when the initiator repeats the write
transaction with the same address, command, data, and byte enable bits as the delayed write command
that is at the head of the posted data queue. Note that the parity bit is not compared when determining
whether the transaction matches those in the delayed transaction queues.
Two cases must be considered:
When parity error is detected on the initiator bus on a subsequent re-attempt of the transaction and
was not detected on the target bus
When parity error is forwarded back from the target bus
For downstream delayed write transactions, when the parity error is detected on the initiator bus and the
bridge has write status to return, the following events occur:
Bridge first asserts P_TRDY# and then asserts P_PERR# two cycles later, if the primary interface
parity-error-response bit is set in the command register.
Bridge sets the primary interface parity-error-detected bit in the status register.
Because there was not an exact data and parity match, the write status is not returned and the
transaction remains in the queue.
Similarly, for upstream delayed write transactions, when the parity error is detected on the initiator bus
and the bridge has write status to return, the following events occur:
Bridge first asserts S_TRDY# and then asserts S_PERR# two cycles later, if the secondary
interface parity-error-response bit is set in the bridge control register (offset 3Ch).
Bridge sets the secondary interface parity-error-detected bit in the secondary status register.
Because there was not an exact data and parity match, the write status is not returned and the
transaction remains in the queue.
For downstream transactions, where the parity error is being passed back from the target bus and the
parity error condition was not originally detected on the initiator bus, the following events occur:
Bridge asserts P_PERR# two cycles after the data transfer, if the following are both true:
The parity-error-response bit is set in the command register of the primary interface.
The parity-error-response bit is set in the bridge control register of the secondary interface.
Bridge completes the transaction normally.
07-0067
Page 44 of 82
March 20, 2007 – Revision 1.01