PT7C4502 Datasheet, PDF (5/6 Pages) Pericom Semiconductor Corporation – PLL Clock Multiplier

PT7C4502
PLL Clock Multiplier
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AC Electrical Characteristics
(V_CC = 3.3V±0.3V, T_A = -40 ~ 85ºC, unless otherwise noted)
Sym.
Parameter
Test Condition
Pin
Min. Typ. Max. Unit
f_IN
Input Frequency
Crystal
ICLK
5
-
30
MHz
f_OUT
Output frequency
Vcc: 3.0 to 3.6V
CLK
20
-
180 MHz
t_r
Output clock rise time
t_f
Output clock fall time
Duty Output clock duty cycle
PLL bandwidth
0.8 to 2.0V, 15pF load
CLK
-
1
-
ns
2.0 to 0.8V, 15pF load
CLK
-
1
-
ns
At Vcc/2, below
160MHz
CLK
45
50
55
%
At Vcc/2, 160MHz to
180MHz
CLK
40
60
%
-
-
10
-
-
kHz
Output enable time
OE high to output on
-
-
-
50
ns
Output disable time
OE low to tri-state
-
-
-
50
ns
Period Jitter
100MHz~180MHz
CLK
-
50
100
ps
(V_CC = 5.0V±0.5V, T_A = -40 ~ 85ºC, unless otherwise noted)
Sym.
Parameter
Test Condition
f_IN
Input Frequency
Crystal
f_OUT
Output frequency
t_r
Output clock rise time
t_f
Output clock fall time
Duty Output clock duty cycle
PLL bandwidth
Vcc: 4.5 to 5.5V
20%Vcc to 80%Vcc,
15pF load
20%Vcc to 80%Vcc,
15pF load
At Vcc/2, below
160MHz
At Vcc/2, 160MHz to
180MHz
-
Output enable time
OE high to output on
Output disable time
OE low to tri-state
Period Jitter
100MHz~180MHz
Pin
ICLK
CLK
CLK
CLK
CLK
CLK
-
-
-
CLK
Min.
5
20
Typ.
-
-
Max.
30
180
Unit
MHz
MHz
-
1.2
-
ns
-
1.2
-
ns
45
50
55
%
40
60
%
10
-
-
kHz
-
-
50
ns
-
-
50
ns
-
50
100
ps
Test circuits
1>Load circuit for output clock duty cycle, rise and fall time Measurement
From Output
Under Test
33om
15pF
2>Timing Definitions for output clock rise and fall time Measurement
2014-09-0002
PT0140-6
09/23/14
5