PT7C4502 Datasheet, PDF (2/6 Pages) Pericom Semiconductor Corporation – PLL Clock Multiplier

PT7C4502
PLL Clock Multiplier
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Pin/Pad Configuration
1520um
Part No.
OE
X1 -ICLK
X2
AVDD DVDD
S1
AGND
DGND
CLK S0
Pin/Pad Description
Pin Name Pad Name
X1/ICLK X1-ICLK
X2
S0
S1
VCC
GND
OE
CLK
AVDD
DVDD
AGND
DGND
Type
I
O
I
I
I
O
P
P
P
P
Description
Crystal connection or clock input.
Crystal connection. Leave unconnected for clock input.
Multiplier select pin 0. Connect to Vcc or float.
Multiplier select pin 1. Connect to GND or float. Internal pull-up.
Output Enable. Tri-states CLK output when low.
Clock output.
Analog Power.
Digital power.
Analog Ground
Digital ground.
Pad Coordinate File
Pad Name X Coordinate Y Coordinate Pad Name X Coordinate Y Coordinate
X1-ICLK
120.90
892.90
CLK
1098.90
118.60
X2
120.90
641.50
S0
1322.10
118.60
S1
117.70
401.10
DVDD
1303.50
973.30
AGND
111.50
225.80
AVDD
1063.10
973.30
DGND
698.40
118.60
OE
470.70
981.70
Note: Substrate is connected to GND.
Die Size: 1670m*1180m (Including scribe line size 150m*80m.)
Die Thickness: PT7C4502DE: 35025m without coating; PT7C4502-2WF: 22020m with coating
Pad Size: 75m*75m
2014-09-0002
S1
S0
0
M ^{Note 2}
0
1 ^{Note 3}
1 ^{Note 3}
1
M ^{Note 2}
1
Note 1: CLK output frequency=ICLK×2;
2. M=Leave unconnected (self-biases to Vcc/2);
3. Internal pull-up on S1, unconnected = 1
2
CLK
×2^{Note 1}
×3
×4 ^(default)
×5
PT0140-6
09/23/14