PT7C4502 Datasheet, PDF (1/6 Pages) Pericom Semiconductor Corporation – PLL Clock Multiplier

PT7C4502
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PLL Clock Multiplier
Features
 Low cost frequency multiplier
 Zero ppm multiplication error
 Input crystal frequency of 5 - 30 MHz
 Input clock frequency of 4 - 50 MHz
 Output clock frequencies up to 180 MHz
 Period jitter 50ps (100~180MHz)
 Duty cycle of 45/55% up to 160MHz
 Operating voltages of 3.0 to 5.5V
 Tri-state output for board level testing
 Die form, Wafer form
Applications
 Used for crystal oscillator
Description
The PT7C4502 is a high performance frequency
multiplier, which integrates Analog Phase Lock Loop
techniques.
The PT7C4502 is the most cost effective way to
generate a high quality, high frequency clock output
from a lower frequency crystal or clock input. It is
designed to replace crystal oscillators in most electronic
systems, clock multiplier and frequency translation.
Using Phase-Locked-Loop (PLL) techniques, the
device uses a standard fundamental mode, inexpensive
crystal to produce output clocks up to 180 MHz.
The complex Logic divider is the ability to
generate nine different popular multiplication factors,
allowing one chip to output many common frequencies.
The device also has an Output Enable pin that tri-
states the clock output when the OE pin is taken low.
This product is intended for clock generation and
frequency translation with low output jitter (variation in
the output period)
Block Diagram
S0
S1
X1/ICLK
X2
PLL Clock Synthesis
and
Control Circuit
Crystal
Oscillator
Output
Buffer
CLK
V_CC
GND
2014-09-0002
PT0140-6
09/23/14
1