PI2EQX4402D_12 Datasheet, PDF (4/7 Pages) Pericom Semiconductor Corporation – 2.5 Gbps x2 Lane Serial PCI Express Repeater/Equalizer with Signal Detect feature

PI2EQX4402D
2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer
with Signal Detect feature
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature........................................................ –65°C to +150°C
Supply Voltage to Ground Potential.................................... –0.5V to +2.5V
DC SIG Voltage..........................................................–0.5V to V_DD +0.5V
Current Output ................................................................-25mA to +25mA
Power Dissipation Continous.......................................................... 800mW
Operating Temperature.............................................................. 0 to +70°C
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
AC/DC Electrical Characteristics for 2.5 Gbps Quad Repeater/Equalizer (V_DD = 1.8 ±0.1V)
Symbol
Parameter
Conditions
Min. Typ. Max.
EN = LVCMOS Low
0.1
Ps
Supply Power
EN = LVCMOS High
0.6
Latency
From input to output
2.0
Units
W
ns
CML Receiver Input
V_RX-DIFFP-P
Differential Input Peak-to-
peak Voltage
V_RX-CM-ACP
AC Peak Common Mode
Input Voltage
V_TH-
Z_RX-DIFF-DC
Signal Detect Threshold
DC Differential Input
Impedance
Z_RX-DC
DC Input Impedance
E_{N_X} = High
0.175
1.200 V
150 mV
120 175 mV
80 100 120
Ω
40
50
60
Equalization
J_RS
Residual Jitter^(1,2)
J_RM
Random Jitter^(1,2)
Total Jitter
Deterministic jitter
0.3
Ulp-p
0.2
1.5
psrms
Notes
1. K28.7 pattern is applied differentially at point A as shown in Figure 1.
2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum
deterministic jitter. Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or
equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or
its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. Jitter is measured at
0V at point C of Figure 1.
12-0256
4
PS8875C
07/17/07