PI2EQX4402D_12 Datasheet, PDF (2/7 Pages) Pericom Semiconductor Corporation – 2.5 Gbps x2 Lane Serial PCI Express Repeater/Equalizer with Signal Detect feature

Pin Description
Pin #
B1, F1, D2, E2,
B3, F3, H4, B8,
F8, B10, F10
Pin Name
V_DD
C3
AI+
D3
E1, J1, F2, E3, J3,
H7, E8, J8, D9,
E9, F9, E10, J10
C8
AI-
GND
BI+
D8
BI-
G3
CI+
H3
CI-
G8
DI+
H8
A3, B4, B5
A4, C4, C5
G2, J2, J4
H2, K2, J5
B6, A5
C6, A6
K3, K4
J6, J9
B7, A7
C7, A8
K9, G9
K10, H9
C10
DI-
SEL[0:
2]_A
SEL[0:2]_B
SEL[0:2]_C
SEL[0:2]_D
SEL[3:4]_A
SEL[3:4]_B
SEL[3:4]_C
SEL[3:4]_D
SEL[5:6]_A
SEL[5:6]_B
SEL[5:6]_C
SEL[5:6]_D
AO+
D10
AO-
C1
BO+
D1
BO-
G10
CO+
H10
CO-
I/O
PWR
I
I
PWR
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
PI2EQX4402D
2.5Gbps x2 Lane Serial PCI Express Repeater / Equalizer
with Signal Detect feature
Description
1.8V Supply Voltage
Positive CML Input Channel A with internal 50Ω pull down during normal operation
(EN_A=1). When EN_A=0, this pin is high impedance.
Negative CML Input Channel A with internal 50Ω pull down during normal operation
(EN_A=1). When EN_A=0, this pin is high impedance.
Supply Ground
Positive CML Input Channel B with internal 50Ω pull down during normal operation
(EN_B=1). When EN_B=0, this pin is high impedance.
Negative CML Input Channel B with internal 50Ω pull down during normal operation
(EN_B=1). When EN_B=0, this pin is high impedance.
Positive CML Input Channel C with internal 50Ω pull down during normal operation
(EN_C=1). When EN_C=0, this pin is high impedance.
Negative CML Input Channel C with internal 50Ω pull down during normal operation
(EN_C=1). When EN_C=0, this pin is high impedance.
Positive CML Input Channel D with internal 50Ω pull down during normal operation
(EN_D=1). When EN_D=0, this pin is high impedance.
Negative CML Input Channel D with internal 50Ω pull down during normal operation
(EN_D=1). When EN_D=0, this pin is high impedance.
Selection pins for equalizer (see Amplifier Configuration Table)
w/ 50KΩ internal pull up
Selection pins for amplifier (see Amplifier Configuration Table)
w/ 50KΩ internal pull up
Selection pins for De-Emphasis (See De-Emphasis Configuration Table)
w/ 50KΩ internal pull up
Positive CML Output Channel A internal 50Ω pull up during normal operation and
2KΩ pull up otherwise.
Negative CML Output Channel A with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
Positive CML Output Channel B with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
Negative CMLOutput Channel B with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
Positive CMLOutput Channel C with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
Negative CMLOutput Channel C with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
12-0256
2
PS8875C
07/17/07