PI2EQX4402D_12 Datasheet, PDF (1/7 Pages) Pericom Semiconductor Corporation – 2.5 Gbps x2 Lane Serial PCI Express Repeater/Equalizer with Signal Detect feature

PI2EQX4402D
2.5 Gbps x2 Lane Serial PCI Express Repeater/Equalizer
with Signal Detect feature
Features
• Two High Speed PCI Express lanes
• Supports PCI Express data rates (2.5 Gbps) on each lane
• Adjustable Transmiter De-Emphasis & Amplitude
• Adjustable Receiver Equalization
• Input Signal Level Detect & Output Squelch on all Channels
• Two Spread Spectrum Reference Clock Buffer Outputs
• 100Ω Differential CML I/O’s
• Low Power (100mW per Channel)
• Standby Mode – Power Down State
• V_DD Operating Range: 1.8V +/-0.1V
• Packaging (Pb-free & Green): 84-ball LFBGA (NB84)
Block Diagram
CML
xI+
xI-
SEL [0:2]
EN_x
Equalizer
Limiting
Amp
CML
xO+
xO-
Power
Management
SEL [3:4]_x SEL [5:6]_x
-- Repeated 4 times --
Description
Pericom Semiconductor’s PI2EQX4402D is a low power,
PCI Express compliant signal Re-Driver. The device provides
programmable equalization, amplification, and de-emphasis
by using 7 select bits, SEL[0:6], to optimize performance
over a variety of physical mediums by reducing Inter-symbol
interference. PI2EQX4402D supports four 100-ohm Differential
CML data I/O’s between the Protocol ASIC to a switch fabric,
across a backplane, or extends the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the PCI Express signal before the Re-Driver.
Whereas the integrated de-emphasis circuitry provides flexibility
with signal integrity of the PCI Express signal after the Re-
Driver.
A low-level input signal detection and output squelch function
is provided for all four channels. Each channel operates fully
independantly. When a channel is enabled (EN_x=1) and
operating, that channel input signal level (on xl+/-) determines
whether the output is enabled. If the input level of the channel
falls below the active threshold level (Vth-) then the output driver
switches off, and the pin is pulled to VDD via a high impedance
resistor.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX4402D also provides power management Stand-by mode
operated by an Enable pin. A differential clock buffer is provided
for test and other system requirements. This clock function is not
used by the data channels.
Pin Description (Top View)
1
2
3
4
5
6
7
8
9
10
A SD_C SD_D SEL0_A SEL0_B SEL4_A SEL4_B SEL6_A SEL6_B EN_A EN_B
B VDD SD_B VDD SEL1_A SEL2_A SEL3_A SEL5_A VDD EN_C VDD
C BO+ SD_A AI+ SEL1_B SEL2_B SEL3_B SEL5_B BI+ EN_D AO+
D BO– VDD
AI–
E GND VDD GND
84-Ball LFBGA
BI– GND AO–
GND GND GND
F VDD GND VDD
VDD GND VDD
G DO+ SEL0_C CI+
DI+ SEL6_C CO+
CKIN-
CKIN+
Buffer
IREF
EN_CLK
OUT0-
OUT0+
OUT1-
OUT1+
H DO– SEL0_D CI–
VDD CKIN+ CKIN– GND DI– SEL6_D CO–
J GND SEL1_C GND SEL2_C SEL2_D SEL3_D IREF GND SEL4_D GND
K EN_CLK SEL1_D SEL3_C SEL4_C OUT0+ OUT0– OUT1+ OUT1– SEL5_C SEL5_D
12-0256
1
PS8875C
07/17/07