PT7C4372A Datasheet, PDF (20/30 Pages) Pericom Semiconductor Corporation – Real-time Clock Module

PT7C4372A/4372C
Real-time Clock Module (I²C Bus)
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2) Level mode:
One second, one minute or one month may be selected for an interrupt cycle. Counting up of seconds is matched with falling edge
of interrupt output.
CTFG bit
/INTA or /INTB pins
(/INTB only for PT7C4372A)
Write 0 to CTFG
Second count-up
Second count-up
Write 0 to CTFG
Second count-up
3) When the time trimming circuit is used, periodic interrupt cycle changes every 20 seconds.
Pulse mode: The period during which the output pulse is low can be adjusted backward or forward up to ±3.784ms (±3.875ms
when 32.000kHz crystal is used).
For example, the duty for the 1-Hz setting can be adjusted ±0.3784% (or ±0.3875% when 32.000kHz crystal is
used) from 50%.
Level mode: a one-second period can be adjusted backward or forward up to ±3.784 ms (±3.875ms when 32.000kHz crystal
is used).
Various Detection Function
PT7C4372A/C detection function includes oscillation stop detection as well as reporting of detection results in corresponding bits
of Control 2 register.
The status of the power supply, oscillation circuit, and clock can be confirmed by checking these results.
*Note with caution that detection functions may not operate correctly when power flickers occur.
Related register
Addr.
Function
F Control 2
Bit 7
-
Bit 6
-
Bit 5
/12, 24
Bit 4
ADJ or
XSTP
Bit 3
/CLEN
Bit 2
CTFG
Bit 1
AAFG
Bit 0
BAFG
Oscillation stop detection
When read control register is 2 bit 4, this bit is as XSTP bit sensing oscillator halt. This bit is as 30 second adjust bit when write.
XSTP Data
Description
Read
0 Ordinary oscillation.
1 Oscillator halts sensing.
Default
This bit senses the oscillator halt. When oscillation is halted after initial power on from 0V or drop in supply voltage, the bit is set
to “1” and remains to be “1” after it is restarted. This bit may be used to judge validity of clock and calendar count data after
power on or supply voltage drop. When this bit is set to “1”, the Time Trimming register, Control 1 register, /CLEN and TEST
bits are reset to “0”. /INTA will stop output and the /INTB will output 32-kHz clock pulses. This bit is set to “0” by setting the
control register 2 during ordinary oscillation.
12-07-0001
PT0150-8 07/04/12
20