PI3HDMI101ZHEX Datasheet, PDF (2/14 Pages) Pericom Semiconductor Corporation – 1:1 Active HDMI™ ReDriver™ with Optimized Equalization & I2C Buffer

ADVANCE INFORMATION - COMPANY CONFIDENTIAL
PI3HDMI101
1:1 Active HDMI^TM Redriver with
Optimized Equalization & I²C Buffer
Pin Configuration
EQ_S0
EQ_S1
GND
IN_CLK–
IN_CLK+
VDD
IN_D0–
IN_D0+
GND
IN_D1–
IN_D1+
VDD
IN_D2–
IN_D2+
GND
Rx_Sense
DCC_EN
1 ^42414039 38
2
37
3
36
4
35
5
34
6
33
7
32
8
31
9 GND 30
10
29
11
28
12
27
13
26
14
25
15
24
16
23
17
22
18192021
SCL_T
VDD
GND
OUT_CLK–
OUT_CLK+
VDD
OUT_D0–
OUT_D0+
GND
OUT_D1–
OUT_D1+
VDD
OUT_D2–
OUT_D2+
GND
VDD
OC_S3
TMDS Receiver Block
Each high speed data and clock input has the same integrated equalization that can eliminate deterministic
jitter caused by input traces or cables. All activity can be configured using pin strapping. The Rx block is
designed to receive all relevant signals directly from the HDMI™ connector without any additional circuitry,
3 High speed TMDS data, 1 pixel clock, and DDC signals. Pixel clock channel has following termination
scheme for Rx Sense support.
250K ohm
AV _DD
R2
Control
Rx Sense
L
H
R₂ switch is open, CLK+/-
termination is 250k
R₂ switch is closed, CLK+/-
termination is 50
CLK+/-
Rx Sense
Although the TMDS clock input channel (pin
4 and 5) has different termination scheme
when port is off, user can still connect TMDS
R1
data channels to these pins for better layout if
required. Any of the 4 differential inputs and
outputs can have data or clock signals passing
through.
All trademark⁰s⁹a^-r⁰e⁰p⁵ro⁵perty of their respective owners.
2
PS8924C
10/05/09