PT7C4363 Datasheet, PDF (11/22 Pages) Pericom Semiconductor Corporation – Real-time Clock Module (I2C Bus)

Data Sheet
PT7C4363
Real-time Clock Module (I²C Bus)
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Alarm Function
Related register
Function
Register definition
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01 Control/status 2
-
-
-
TI/TP
AF
TF
AIE
TIE
02 Seconds
OSF
S40
S20
S10
S8
S4
S2
S1
03 Minutes
×
M40
M20
M10
M8
M4
M2
M1
04 Hours
×
×
H20
H10
H8
H4
H2
H1
05 Dates
×
×
D20
D10
D8
D4
D2
D1
06 Days of the week
×
×
×
×
×
W4
W2
W1
09 Alarm: Minutes
AE
M40
M20
M10
M8
M4
M2
M1
0A Alarm: Hours
AE
×
H20
H10
H8
H4
H2
H1
0B Alarm: Dates
AE
×
D20
D10
D8
D4
D2
D1
0C Alarm: Weekday
AE
×
×
×
×
W4 ^W2
W1
When one or more of these registers are loaded with a valid minute, hour, day or weekday and its corresponding bit Alarm Enable
(AE) is logic 0, then that information will be compared with the current minute, hour, day and weekday. When all enabled
comparisons first match, the Alarm Flag (AF) is set. AF will remain set until cleared by software. Once AF has been cleared it
will only be set again when the time increments to match the alarm condition once more. Alarm registers which have their bit AE
at logic 1 will be ignored.
EXT_CLK Test Mode and POR override
1. EXT_CLK Test Mode
A test mode is available which allows for on-board testing. In such a mode it is possible to set up test conditions and control the
operation of the RTC. The test mode is entered by setting bit TEST1 in control/status1 register. Then pin SQW becomes an input.
The test mode replaces the internal 64 Hz signal with the signal applied to pin SQW. Every 64 positive edges applied to pin SQW
will then generate an increment of one second.
The signal applied to pin SQW should have a minimum pulse width of 300 ns and a minimum period of 1000 ns. The internal 64
Hz clock, now sourced from SQW, is divided down to 1 Hz by a 2⁶ divide chain called a pre-scaler. The pre-scaler can be set into
a known state by using bit STOP. When bit STOP is set, the pre-scaler is
reset to 0 (STOP must be cleared before the pre-scaler can operate again).
From a STOP condition, the first 1 second increment will take place after 32 positive edges on SQW. Thereafter, every 64 positive
edges will cause a 1 second increment.
Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no
assumption as to the state of the pre-scaler can be made.
PT0207(07/05)
11
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