PI3HDMI412FT-A Datasheet, PDF (1/12 Pages) Pericom Semiconductor Corporation – 2:1 Mux/DeMux High Bandwidth (> 5 Gbps) HDMI 1.3 Compliant Signal Switch

PI3HDMI412FT-A
2:1 Mux/DeMux High Bandwidth (> 5 Gbps)
HDMI 1.3 Compliant Signal Switch
Features
• 4-Differential Channel 2:1 Mux/DeMux
• HDMI 1.1, 1.2, and 1.3 compatible
• Allowable Data Rate: > 5.0 Gbps
• Supports both AC coupled and DC coupled signals
• Switching speed: 4ns
• Isolation: -40dB @ 2.0 Gbps
• Crosstalk: -31dB @ 2.0 Gbps
• ESD: Data bits @ 8kV contact, select bit @ 2kV HBM
• Low bit-to-bit skew
• Enable/Disable Time: 9ns
• Bidirectional
• Packaging (Pb-free & Green):
— 42-pin TQFN (ZH42)
— 48-pin BQSOP (B48)
Block Diagram
V_DD
Description
Pericom Semiconductor’s PI3HDMI series of switch circuits
are targeted for high-resolution video networks that are based
on DVI/HDMI standards, and TMDS signal processing. The
PI3HDMI412FT-A is an 8- to 4-Channel Mux/DeMux Switch. The
device multiplexes differential signals to one of two corresponding
outputs. The switch is bidirectional and offers little or no attenua-
tion of the high-speed signals at the outputs. It is designed for low
bit-to-bit skew and high channel-to-channel noise isolation.
The allowable data rate of 5.0Gbps provides the resolution required
by the next generation HDTV and PC graphics. Three differential
channels are used for data (video signals for DVI or audio/video
signals for HDMI), and one differential channel is used for Clock
for decoding the TMDS signals at the outputs.
Due to its integrated pull-up resistors, the product has been designed
specifically for applications where the part is used as a 2 to 1 mux,
not 1 to 2 demux. Therefore, Pericom only recommends the part
to be used as a 2 to 1 mux when dealing with HDMI signals. Even
though the passive circuitry does not eliminate the bi-directional
functionality, it is not ideal when used with HDMI signals. If DVI
are used, either direction can be used.
Pin Description
42-pin TQFN
48-pin BQSOP
D₀₊
D_0-
D₁₊
D_1-
D₂₊
D_2-
D₃₊
D_3-
SEL
VSS
1
D_0+A
D_0-A
D_1+A
D_1-A
D_2+A
D_2-A
D_3+A
D_3-A
D_0+B
D_0-B
D_1+B
D_1-B
D_2+B
D_2-B
D_3+B
D_3-B
VDD
2
V_SS
V_DD
D0+
D0-
V_SS
D1+
D1-
V_DD
SEL
V_SS
42 41 40 39
1
38
2
37
3
36
4
35
5
34
6
33
7
32
8
31
9
V_SS
30
10
29
D0+^A
D0-^A
D1+^A
D1-^A
D2+^A
D2-^A
D3+^A
D3-^A
VDD
D0+^B
VSS
VDD
VSS
D0+
D0-
V_SS
D1+
D1-
V_SS
VDD
SEL
3
4
5
6
7
8
9
10
11
12
13
D2+ 11
D2- 12
28 D0-^B
27 D1+^B
V_SS
D2+
14
15
V_SS 13
26 D1-^B
D2-
16
D3+ 14
25 D2+^B
V_SS
17
D3- 15
24 D2-^B
D3+
18
V_DD 16
V_SS 17
23 D3+^B
D3-
19
22 D3-^B
V_SS
20
18 19 20 21
V_DD
21
V_SS
22
V_DD
23
V_DD
VSS
24
48
VDD
47
VSS
46
D0^+A
45
D0-^A
44
D1^+A
43
D1-^A
42
VSS
41
D2^+A
40
D2-^A
39
D3^+A
38
D3^-A
37
VSS
36
VDD
35
D0^+B
34
D0-^B
33
D1^+B
32
D1-^B
31
V_SS
30
D2^+B
29
D2-^B
28
D3^+B
27
D3^-B
26
VSS
25
VDD
06-0309
1
PS8831C
12/18/06