PI2EQX3201BL Datasheet, PDF (1/5 Pages) Pericom Semiconductor Corporation – 3.0Gbps 2 Differential Channel SATA i/m ReDriver with Equalization, De-emphasis and OOB

PI2EQX3201BL
3.0Gbps 2 Differential Channel SATA i/m ReDriver^TM
with Equalization, De-emphasis and OOB
Features
• SATA2 i/m, extended SATA2
• Two Pairs of 3.0Gbps differential signal
• Adjustable Transmitter Emphasis & Amplitude
• Adjustable Receiver Equalization
• 100-Ohm Differential CML I/O’s
• Input signal level detect and squelch for each channel
• Low Power (100mW per Channel)
• Stand-by Mode – Power Down State
• V_DD Operating Range: 1.5V to 1.8V
• Packaging (Pb-free & Green):
— 36-pad TQFN (ZF36)
Description
Pericom Semiconductor’s PI2EQX3201BL is a low power,
signal ReDriver. The device provides programmable
equalization, amplification, and de-emphasis by using 4 select
bits, SEL[0:3], to optimize performance over a variety of
physical mediums by reducing Inter-Symbol Interference.
PI2EQX3201BL supports two 100-Ohm Differential CML data
I/O’s between the Protocol ASIC to a switch fabric, across a
backplane, or to extend the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the signal before the re-driver. Whereas the
integrated de-emphasis circuitry provides flexibility with signal
integrity of the signal after the re-driver.
A low-level input signal detection and output squelch function
is provided for each channel. Each channel operates fully
independantly. When a channel is enabled (EN_x=1) and
operating, that channels input signal level (on xI+/-) determines
whether the output is enabled. If the input level of the channel
falls below the active threshold level (Vth-) then the outputs are
driven to the common mode voltage.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX3201BL also provides power management Stand-by
mode operated by a Bus Enable pin.
Block Diagram
Signal�Detection
CML
xl+
xl-
SEL[0:1]_X
Equalizer
Limiting
Amp
CML
xO+
xO-
SEL2_x SEL3_x
EN_X
Power
Management
10-0220
Repeated 2 Times -
Pin Description (Top-Side View)
36 35 34 33 32 31 30 29
V_DD
1
28
AI⁺
2
27
AI^-
3
26
GND 4
25
V_DD
5
V_DD
6
GND
24
23
B₀₊
7
22
B_0-
8
21
GND ⁹
20
V_DD 10
19
11 12 13 14 15 16 17 18
V_DD
A₀₊
A_0-
GND
GND
V_DD
BI⁺
BI^-
GND
NC
1
PS9003A 09/07/10