PI29FCT520T Datasheet, PDF (1/5 Pages) Pericom Semiconductor Corporation – FAST CMOS MULTILEVEL PIPELINE REGISTERS

PI29FCT520T/2520T
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Fast CMOS Multilevel Pipeline Registers
Product Features:
• PI29FCT520T and PI29FCT521T are pinout and
function compatible with IDT29FCT520/521,
QS29FCT520/521 and AMD's Am29520/521
• Four 8-bit high-speed registers
• Hold, Transfer, and load instructions
• Dual two-level or single four-level pipeline operation
• TTL input and output levels, reducing problematic
"ground bounce"
• High output drive
IOL = 48 mA
• Extremely low static power (1 mW, typ.)
• Industrial operating temperature range: –40°C to +85°C
• FCT (2xxxT) has a 25Ω series resistor.
• Packages available:
– 24-pin 300 mil wide plastic DIP (P24)
– 24-pin 150 mil wide plastic QSOP (Q24)
– 24-pin 150 mil wide plastic TQSOP (R24)
– 24-pin 300 mil wide plastic SOIC (S24)
Logic Block Diagram
Product Description:
Pericom Semiconductor’s PI29FCT series of logic circuits are
pro-duced in the Company’s advanced 0.8 micron CMOS
technology, achieving industry leading speed grades.
The PI29FCT520T/2520T and PI29FCT521T are multilevel
pipeline registers containing four 8-bit positive triggered registers
which can be configured as a dual 2-level or a single 4-level
pipeline. These products are designed for use as temporary storage
or for storage delays in pipelined systems.
The PI29FCT521T differs from the PI29FCT520T/2520T only in
the way data is loaded into and between registers in the dual 2-level
operation. When data is entered into the first level (I = 2 or I = 1)
of the PI29FCT520T/2520T, the existing data in the first level is
moved to the second level. In the PI29FCT521T, these instructions
simply overwrite the data in the first level. Transfer of data to the
second level is achieved using the 4-level shift instruction (I = 0)
causing the first level to change. In either part, I = 3 shift
instruction puts the registers on hold.
Device models available upon request.
D0–D7
8
FCT520.pm6
2
I0,I1
1
CLK
REGISTER
CONTROL
2
S0,S1
1
MUX
OCTAL
REGISTER A1
OCTAL
REGISTER B1
OCTAL
REGISTER A2
OCTAL
REGISTER B2
MUX
OE
1
8
Y0–Y7
12/18/96, 4:44 PM
PS2002B 12/10/96