PE3341 Datasheet, PDF (5/17 Pages) Peregrine Semiconductor Corp. – 2700 MHz Integer-N PLL with Field-Programmable EEPROM Features

PE3341
Product Specification
Table 6. AC Characteristics
V_DD = 3.0 V, -40° C < T_A < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Control Interface and Registers (see Figure 4)
fClk
Serial data clock frequency
(Note 1)
tClkH
Serial clock HIGH time
tClkL
Serial clock LOW time
tDSU
Data set-up time to Clock rising edge
tDHLD
Data hold time after Clock rising edge
tPW
S_WR pulse width
tCWR
Clock rising edge to S_WR rising edge
tCE
Clock falling edge to E_WR transition
tWRC
S_WR falling edge to Clock rising edge
tEC
E_WR transition to Clock rising edge
EEPROM Erase/Write Programming (see Figures 5 & 6)
tEESU
tEEPW
tVPP
EELoad rising edge to VPP rising edge
VPP pulse width
VPP pulse rise and fall times
Main Divider (Including Prescaler)
(Note 2)
FIn
Operating frequency
FIn
Operating frequency
Speed-grade option (Note 3)
PFIn
Input level range
External AC coupling
Main Divider (Prescaler Bypassed)
FIn
Operating frequency
(Note 4)
PFIn
Input level range
External AC coupling (Note 4)
Reference Divider
fr
Operating frequency
(Note 5)
Pfr
Reference input power (Note 4)
Single ended input
Phase Detector
fc
Comparison frequency
(Note 6)
SSB Phase Noise (Fin = 1.3 GHz, fr = 10 MHz, fc = 1.25 MHz, LBW = 70 kHz, VDD = 3.0 V, Temp = -40° C)
100 Hz Offset
1 kHz Offset
Min
30
30
10
10
30
30
30
30
30
500
25
1
300
300
-5
50
-5
-2
Max
10
30
2700
3000
5
270
5
100
20
-75
-85
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
MHz
MHz
dBm
MHz
dBm
MHz
dBm
MHz
dBc/Hz
dBc/Hz
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fClk
specification.
Rise and fall times of the VPP programming voltage pulse must be greater than 1 µs.
The maximum frequency of operation can be extended to 3.0 GHz by ordering a special speed-grade option. Please refer to Table 14,
Ordering Information, for ordering details.
CMOS logic levels can be used to drive FIn input if DC coupled and used in Prescaler Bypass mode. Voltage input needs to be a minimum
of 0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns. No minimum
frequency limit exists when operated in this mode.
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum
phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns.
Parameter is guaranteed through characterization only and is not tested.
Document No. 70-0053-04 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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