PE3341 Datasheet, PDF (2/17 Pages) Peregrine Semiconductor Corp. – 2700 MHz Integer-N PLL with Field-Programmable EEPROM Features

PE3341
Product Specification
Figure 2. Pin Configurations (Top View)
V_DD 1
GND ²
ENH 3
S_WR ⁴
Data 5
Clock 6
GND 7
FSel ⁸
E_WR 9
V_PP ¹⁰
V_DD ¹¹
F_in ¹²
24-lead TSSOP
24 f_r
23 _GND
22 EESel
21 _N/C
20 CP
19 V_DD
18 Dout
17 _LD
16 EELoad
15 _Cext
14 _GND
13 _Fin
S_WR 1
Data 2
Clock 3
FSel 4
E_WR 5
20-lead QFN
4x4 mm
Exposed Solder Pad
(Bottom Side)
15 CP
14 V_DD
13 Dout
12 LD
11 EELoad
Figure 3. Package Types
24-lead TSSOP, 20-lead QFN
Table 2. Pin Descriptions
Pin No.
TSSOP
1
2
3
Pin No.
QFN
19
20
Pin Name Type
VDD
GND
(Note 1)
(Note 2)
ENH
Input
4
1
S_WR
Input
5
2
Data
Input
6
3
Clock
Input
7
GND
(Note 2)
8
4
FSel
Input
9
5
E_WR
Input
10
6
VPP
Input
11
7
VDD
(Note 1)
12
8
Fin
Input
13
9
Fin
Input
14
GND
(Note 2)
15
10
CEXT
Output
16
11
EELoad
Input
17
12
LD
Output, OD
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.
Ground.
Enhancement mode control line. When asserted LOW, enhancement register bits are
functional. Internal 70 kΩ pull-up resistor.
Secondary Register WRITE input. Primary Register contents are copied to the
Secondary Register on S_WR rising edge. Also used to control Serial Port operation
and EEPROM programming.
Binary serial data input. Input data entered LSB (B0) first.
Serial clock input. Data is clocked serially into the 20-bit Primary Register, the 20-bit
EE Register, or the 8-bit Enhancement Register on the rising edge of Clock. Also used
to clock EE Register data out Dout port.
Ground.
Frequency Register selection control line. Internal 70 kΩ pull-down resistor.
Enhancement Register write enable. Also functions as a Serial Port control line.
Internal 70 kΩ pull-down resistor.
EEPROM erase/write programming voltage supply pin. Requires a 100pF bypass
capacitor connected to GND.
Same as pin 1.
Prescaler input from the VCO.
Prescaler complementary input. A series 50 Ω resistor and DC blocking capacitor
should be placed as close as possible to this pin and connected to the ground plane.
Ground.
Logical “NAND” of PD_U and PD_D terminated through an on-chip, 2 kΩ series
resistor. Connecting CEXT to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
Control line for Serial Data Port, Frequency Register selection, EE Register parallel
loading, and EEPROM programming. Internal 70 kΩ pull-down resistor.
Lock detect output, an open-drain logical inversion of CEXT. When the loop is in lock,
LD is high impedance; otherwise, LD is a logic LOW.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 17
Document No. 70-0053-04 │ UltraCMOS™ RFIC Solutions