PE3341 Datasheet, PDF (3/17 Pages) Peregrine Semiconductor Corp. – 2700 MHz Integer-N PLL with Field-Programmable EEPROM Features

PE3341
Product Specification
Pin No.
TSSOP
18
19
20
Pin No.
QFN
13
14
15
Pin Name Type
Dout
VDD
CP
Output
(Note 1)
Output
Description
Data out function. Dout is defined with the Enhancement Register and enabled with
ENH.
Same as pin 1.
Charge pump output. Sources current is when fc leads fp and sinks current when fc lags
fp.
21
16
N/C
No connection.
22
17
EESel
Input
Control line for Frequency Register selection, EE Register parallel loading, and
EEPROM programming. Internal 70 kΩ pull-up resistor.
23
GND
(Note 2)
Ground.
24
18
fr
Input
Reference frequency input.
Notes 1: VDD pins 1, 11, and 19 (TSSOP) or pins 6, 14 and 19 (QFN), are connected by diodes and must be supplied with the same positive voltage
level.
2: Ground connections are made through the exposed solder pad. The solder pad must be soldered to the ground plane for proper operation.
Table 2. Absolute Maximum Ratings
Symbol Parameter/Conditions Min
VDD
Supply voltage
VI
Voltage on any digital
input
TStg
Storage temperature
range
–0.3
–0.3
–65
Max
+4.0
VDD+0.3
+85
Units
V
V
°C
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC and AC Characteristics table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Table 3. DC Electrical Specifications
Symbol Parameter/Conditions Min
VDD
Supply voltage
TA
Operating ambient
temperature range
2.85
-40
Max
3.15
85
Units
V
°C
Table 4. ESD Ratings
Symbol Parameter/Conditions Min Max Units
VESD
ESD voltage human body
model (Note 1)
1000
V
VESD
(VPP)
ESD voltage human body
model (Note 1)
200
V
Note 1: Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Document No. 70-0053-04 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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