PE3236 Datasheet, PDF (11/15 Pages) Peregrine Semiconductor Corp. – 2200 MHz UltraCMOS-TM Integer-N PLL for Low Phase Noise Applications

PE3236
Product Specification
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Reserved**
Bit 1
Reserved**
Bit 2
Reserved**
Bit 3
Bit 4
Power down
Counter load
Power down of all functions except programming interface.
Immediate and continuous load of counter programming as directed by the Bmode and Smode inputs.
Bit 5
MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Bit 6
Bit 7
Prescaler output
fp, fc OE
Drives the raw internal prescaler output onto the Dout output.
fp, fc outputs disabled.
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (f_p) and the reference
counter (f_c). It has two outputs, namely PD_U,
and PD_D. If the divided VCO leads the divided
reference in phase or frequency (f_p leads f_c),
PD_D pulses “low”. If the divided reference leads
the divided VCO in phase or frequency (f_c leads
f_p), PD_U pulses “low”. The width of either pulse
is directly proportional to phase offset between the
two input signals, f_p and f_c.
PD_U and PD_D drive an active loop filter which
controls the VCO tune voltage. PD_U pulses
result in an increase in VCO frequency and PD_D
results in a decrease in VCO frequency.
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 kΩ resistor. Connecting Cext to an external
shunt capacitor provides integration. Cext also
drives the input of an internal inverting comparator
with an open drain output. Thus LD is an “AND”
function of PD_U and PD_D.
Document No. 70-0026-03 │ www.psemi.com
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
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