MN103SL7 Datasheet, PDF (7/9 Pages) Panasonic Semiconductor – 32-bit Single-chip Microcontroller

MN103SL7 Series
 Features (continued)
 Serial Interface
Serial 1 (Multi master IIC / Full duplex UART / Synchronous serial interface)
Synchronous serial interface
Overrun error detection
Transfer clock source: 1/2, 1/4, 1/16 and 1/64 of timer 0 underflow,
1/2, 1/4, 1/16 and 1/64 of timer 1 underflow,
1/2, 1/4, 1/16 and 1/64 of timer 2 underflow,
1/2, 1/4, 1/16 and 1/64 of timer 3 underflow,
IOCLK/2, IOCLK/4, SBT1 pin
Transfer clock division value selection : Divided by 8, 16
Can be selected as the first bit to be transferred, Any transfer size from 2 to 8 bits can be selected.
Can be continuously transmitted, received or transmitted and received.
Maximum transfer rate: 5.0 Mbps
Full duplex UART
Parity check, Overrun and framing error detection
Transfer clock source: 1/2, 1/4, 1/16, and 1/64 of timer 0 underflow,
1/2, 1/4, 1/16, and 1/64 of timer 1 underflow,
1/2, 1/4, 1/16, and 1/64 of timer 2 underflow,
1/2, 1/4, 1/16, and 1/64 of timer 3 underflow,
IOCLK/2, IOCLK/4
Transfer clock division value selection : Divided by 8, 16
Can be selected as the first bit to be transferred, Any transfer size from 7 to 8 bits can be selected.
Continuous transmission, reception, and transmission/reception
Maximum transfer rate: 300 kbps
Multi master IIC
7, 10-bit slave address is settable
General call communication mode is supported
Transfer clock source: 1/2, 1/4, 1/16, and 1/32 of timer 0 underflow,
1/2, 1/4, 1/16, and 1/32 of timer 1 underflow,
1/2, 1/4, 1/16, and 1/32 of timer 2 underflow,
1/2, 1/4, 1/16, and 1/32 of timer 3 underflow,
IOCLK/2, IOCLK/4
Transfer clock division value selection : Divided by 8
 Power Supply Voltage Detection
Detection level
4.15 V ± 0.25 V (At falling voltage)
4.25 V ± 0.25 V (At rising voltage)
When power supply voltage become equal to detection level, interrupt is generated.
 Auto Reset Circuit
Detection level
3.50 V ± 0.20 V (At falling voltage)
3.65 V ± 0.35 V (At rising voltage)
When power supply voltage is under detection level, reset is generated.
 Clock Monitoring Function
Frequency error of the external high-speed oscillation ( include PLL output) can detect.
When the error is detected, reset is generated.
Ver. AEM
7