MN86063 Datasheet, PDF (6/10 Pages) Panasonic Semiconductor – High-Speed CODEC LSI for Facsimile Images

MN86063
For Communications Equipment
Pin Descriptions (continued)
Image Bus (continued)
Pin No. Symbol
I/O
78
ID15
I/O
79
ID14
Tristate
80
ID13
81
ID12
82
ID11
83
ID10
84
ID9
85
ID8
86
ID7
87
ID6
88
ID5
89
ID4
90
ID3
91
ID2
92
ID1
93
ID0
41
IHREQ
O
42
IHACK
I
49 IREADY
I
52
IMUE
O
Tristate
53
IMLE
O
Tristate
45
IMR
O
Tristate
47
IMW
O
Tristate
55
DSTR0
O
54
DSTR1
O
44
DREQ0
I
43
DREQ1
I
56 DACK0
O
57 DACK1
O
Function Description
Image data. These pins form a bus for bidirectional transfers of image data.
Image bus request. This output pin indicates a request for control of the
image bus.
Image bus acknowledge. This input pin indicates when the chip can seize
control of the image bus.
Image data acknowledge. This input pin indicates the end of the read/
write operation.
Image memory upper byte enable. This output pin specifies whether the
data from pins ID15–ID8 is effective.
Image memory lower byte enable. This output pin specifies whether the
data from pins ID7–ID0 is effective.
Image memory read. This output pin indicates a read from the address on
the image address bus.
Image memory write. This output pin indicates a write to the address on
the image address bus.
DMA start 0. This output indicates that the chip is ready for a DMA
transfer from an I/O device to memory.
DMA start 1. This output indicates that the chip is ready for a DMA
transfer from memory to an I/O device.
DMA request 0. This input pin indicates a request for a DMA transfer
from an I/O device to memory.
DMA request 1. This input pin indicates a request for a DMA transfer
from memory to an I/O device.
DMA acknowledge 0. This output pin gives the response to the DREQ0
signal, initiating a DMA transfer from an I/O device to memory.
DMA acknowledge 1. This output pin gives the response to the DREQ1
signal, initiating a DMA transfer from memory to an I/O device.