MN86063 Datasheet, PDF (5/10 Pages) Panasonic Semiconductor – High-Speed CODEC LSI for Facsimile Images

For Communications Equipment
MN86063
Pin Descriptions (continued)
System Bus (continued)
Pin No. Symbol
I/O
29 REQD0
O
30 REQD1
O
31 ACKC0
I
32 ACKC1
I
33 ACKD0
I
34 ACKD1
I
5 2SYSCLK
I
8 SYSCLK
O
Function Description
DMA transfer input request 0. This output pin indicates a request for data
input on DMA channel 0.
DMA transfer input request 1. This output pin indicates a request for data
input on DMA channel 1.
DMA transfer output acknowledge 0. This input pin accepts the response
to a DMA transfer request with REQC0.
DMA transfer output acknowledge 0. This input pin accepts the response
to a DMA transfer request with REQC1.
DMA transfer input acknowledge 0. This input pin accepts the response
to a DMA transfer request with REQD0.
DMA transfer input acknowledge 0. This input pin accepts the response
to a DMA transfer request with REQD1.
2 system clock. This input pin accepts a clock signal with a frequency
twice that of the system clock.
System clock. This output pin provides a clock signal with half the
frequency of 2SYSCLK.
Image Bus
Pin No. Symbol
60
IA15
61
1A14
62
IA13
63
IA12
64
IA11
65
IA10
66
IA9
67
IA8
68
IA7
69
IA6
70
IA5
71
IA4
72
IA3
73
IA2
74
IA1
75
IA0
I/O
O
Tristate
Function Description
Image address bus. These pins provide an address on the image data bus.