MN86063 Datasheet, PDF (4/10 Pages) Panasonic Semiconductor – High-Speed CODEC LSI for Facsimile Images

MN86063
Pin Descriptions
System Bus
Pin No. Symbol
35
A3
36
A2
37
A1
38
A0
9
D15
10
D14
11
D13
12
D12
13
D11
14
D10
15
D9
16
D8
17
D7
18
D6
19
D5
20
D4
21
D3
22
D2
23
D1
24
D0
26
UBE
I/O
I
I/O
Tristate
I
6
RD
I
7
WR
I
25
CS
I
1
HEX
I
100 RESET
I
2
INTR0
O
Open
corrector
3
INTR1
O
Open
corrector
4
INTR2
O
Open
corrector
27
REQC0
O
28
REQC1
O
For Communications Equipment
Function Description
Address. Address bus for accessing internal registers
Data. Data bus for bidirectional transfers over system bus
Upper byte enable. This input pin specifies whether the data from pins
D15–D8 is effective.
Read. This input pin specifies a read from the specified register.
Write. This input pin specifies a write to the specified register.
Chip select. This input pin specifies access to a register.
Data bus width selection. This input pin specifies the width of the system
data bus: "0" for 16 bits; "1" for 8 bits.
Reset. This input pin resets the internal circuitry, clearing all registers.
Interrupt request 0. This output pin indicates an interrupt request
triggered by the cause given in interrupt register 0 (STIR0)
Interrupt request 1. This output pin indicates an interrupt request
triggered by the cause given in interrupt register 1 (STIR1)
Interrupt request 2. This output pin indicates an interrupt request
triggered by the cause given in DMA transfer interrupt register (DMIR).
DMA transfer output request 0. This output pin indicates a request for
data output on DMA channel 0.
DMA transfer output request 1. This output pin indicates a request for
data output on DMA channel 1.