MN101E50 Datasheet, PDF (6/9 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

MN101E50 Series
 Features (continued)
 Buzzer Output
Output frequency can be selected from fpll-div/2⁹, fpll-div/2¹⁰, fpll-div/2¹¹, fpll-div/2¹², fpll-div/ 2¹³, fpll-div/2¹⁴, fslow/2³,
fslow/2⁴
 A/D converter
10 bits × 12 channels
 Serial Interface: 4 systems
<Serial Interface 0> (Full duplex UART/ Clock synchronous serial interface)
Clock synchronous serial interface
Transfer clock source:
fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4, Timer 0 to 4, Timer A output divided by 1, 2, 4, 8, 16, External clock
MSB/LSB can be selected as the first bit to be transferred, arbitrary size of 1 to 8 bits is selectable.
Continuous transmission, continuous reception, continuous transmission/reception are available.
Full duplex UART
Baud rate timer: selected from Timer 0 to 4, or Timer A
Parity check, overrun error/framing error are detected
Transfer bits of 7 to 8 are selectable
<Serial Interface 1> (Full duplex UART/ Clock synchronous serial interface)
Clock synchronous serial interface
Transfer clock source:
fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4, Timer 0 to 4, Timer A output divided by 1, 2, 4, 8, 16, external clock
MSB/LSB can be selected as the first bit to be transferred, arbitrary size of 1 to 8 bits are selectable.
Continuous transmission, continuous reception, continuous transmission/reception are available.
Full duplex UART
Baud rate timer: selected from Timer 0 to 4, or Timer A
Parity check, overrun error/framing error are detected
Transfer bits of 7 to 8 are selectable
<Serial Interface 2> (Full duplex UART / Clock synchronous serial interface)
Clock synchronous serial interface
Transfer clock source:
fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4, Timer 0 to 4, Timer A output divided by 1, 2, 4, 8, 16, External clock
MSB/LSB can be selected as the first bit to be transferred, arbitrary size of 1 to 8 bits are selectable.
Continuous transmission, continuous reception, continuous transmission/reception are available.
Full duplex UART
Baud rate timer: selected from Timer 0 to 4, or Timer A
Parity check, overrun error/framing error are detected
Transfer bits of 7 to 8 are selectable
<Serial Interface 4> (Multi master IIC/ Clock synchronous serial interface)
Clock synchronous serial interface
Transfer clock source:
fpll-div/2, fpll-div/4, fpll-div/8, fpll-div/32, fs/2, fs/4, Timer 0 to 4, Timer A output divided by 1, 2, 4, 8, 16, External clock
MSB/LSB can be selected as the first bit to be transferred, arbitrary size of 1 to 8 bits are selectable.
Continuous transmission, continuous reception, continuous transmission/reception are available.
Multi master IIC
7-bit or 10-bit slave address can be set.
General call communication mode is supported
 Auto reset circuit
6
Ver. AEM