MN101E50 Datasheet, PDF (2/9 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

MN101E50 Series
 Features
 Memory
ROM capacity: 64 KB
RAM capacity: 4 KB
 Package
LQFP064-P-1414 (14 mm × 14 mm / 0.8 mm pitch)
 Machine Cycle
High-speed mode
0.05 ms / 20 MHz (2.7 V to 5.5 V)
0.125 ms / 8 MHz (1.8 V to 5.5 V)
Low-speed mode
62.5 ms / 32 kHz (1.8 V to 5.5 V)
 Clock Gear Circuit:
Variable internal system clock speed (fosc/1, fosc/2, fosc/4, fosc/16, fosc/64 and fosc/128)
 High-speed Clock (fpll-div) Gear Circuit for peripherals:
Select among "Stop", fpll/1, fpll/2, fpll/4, fpll/8 and fpll/16.
 Oscillation Circuit
High-speed: internal oscillation (frc) or crystal/ceramic (fosc)
Low-speed: crystal/ceramic (fx)
* High-speed internal oscillation: 20 MHz / 16 MHz (selectable)
* 20 MHz can be selected only when internal high-speed oscillator is used without using external high-speed
oscillator or low-speed oscillators.
 Clock Multiplication Circuit
PLL output clock (fpll)
fosc × n (n: 2, 3, 4, 5, 6, 8, 10)
frc/2 × n (n: 4, 5)
* When clock multiplication circuit is not used, fpll = fosc or fpll = frc
 Memory Bank
Data memory space is expandable with the memory bank system. (16 banks with 64 KB each)
Consists of banks for the source address and banks for the destination address.
 Operating Mode
NORMAL Mode (high-speed mode)
PLL Mode
SLOW Mode (low-speed mode)
HALT Mode
STOP Mode
Clock Transition Mode
 Operating Voltage
1.8 V to 5.5 V
 Operating Ambient Temperature:
-40°C to +85°C
2
Ver. AEM