MN89303A Datasheet, PDF (5/11 Pages) Panasonic Semiconductor – SVGA Display Controller

For Information Equipment
MN89303A
Pin Descriptions (continued)
Pin No. Symbol I/O Level
Function Description
102 LCAS
O CMOS Lower Column Address Strobe (LCAS)
This output is the strobe signal for the lower column address latch.
In the 2WE mode, however, it functions as the LWE signal.
103 WE
O CMOS Write Enable
This output is the data write signal. In the 2WE mode, however, it
functions as the UWE signal.
104 to 121 MD[15:0] I/O TTL Memory Data
These pins represent the data bus to the DRAM.
31
BIOSEN
O CMOS BIOS Enable
This output enables ROM BIOS output.
83
BACKON O CMOS Backlight ON
This output requests backlighting.
"L" level: OFF; "H" level: ON
84
LCDON
O CMOS LCD Drive ON
This output requests power-ON for the LCD panel.
"L" level: OFF; "H" level: ON
85
LOGICON O CMOS LCD Logic ON
This output requests power-ON for LCD panel logic circuits.
"L" level: OFF; "H" level: ON
63
LP
O CMOS Line Pulse
This output provides pulses indicating the end of a line of the
LCD panel.
64
FP
O CMOS Frame Pulse
This output provides pulses indicating the start of a frame of the
LCD panel.
62
DISP
O CMOS Display Enable
This output enables the LCD display. An external RAMDAC uses
this signal as a blanking signal. A TFT LCD uses it as an enable
signal.
61
DCLK
O CMOS Data Shift Clock
This pin provides a data shift clock signal for an STN LCD panel.
It also outputs a dot clock signal on a TFT LCD panel or external
RAMDAC display mode.
65 to 72 UD[7:0]
O CMOS Upper Data[7:0]
75 to 82 LD[7:0]
O CMOS Lower Data[7:0]
This pins provide display data.
Usage varies with the LCD panel type.