MN89303A Datasheet, PDF (4/11 Pages) Panasonic Semiconductor – SVGA Display Controller

MN89303A
For Information Equipment
Pin Descriptions
Pin No. Symbol I/O
3 AEN
I
4 SBHE
I
5 IOWR
I
6 IORD
I
7 SMEMW
I
8 SMEMR
I
9 to 10 A[21:20]
I
11 to 30 SA[19:0]
I
35 to 53 SD[15:0] I/O
56 IOCHRDY I/O
57 MEMCS16 O
58 IOCS16
O
32 REFRESH I
88 to 97 MA[9:0]
O
100 RAS
O
101 UCAS
O
Level
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
CMOS
CMOS
CMOS
Function Description
Address Enable
"H" level input from this pin indicates that a DMA transfer is in
progress, so the chip does not respond to I/O access.
Byte High Enable
This input indicates the state of the 16-bit bus.
I/O Write
This input indicates an I/O write request.
I/O Read
This input indicates an I/O read request.
Memory Write
This input indicates a memory write request dedicated for an address
space in the first megabyte (000000 to 0FFFFFH).
Memory Read
This input indicates a memory read request dedicated for an address
space in the first megabyte (000000 to 0FFFFFH).
Address[21:20]
These inputs give the address 21:20.
Address[19:0]
These inputs give the address 19:0.
Data[15:0]
These pins represent the host data bus.
I/O Channel Ready
This pin is "L" level when I/O or memory access is given wait state.
Memory Chip Select 16
This output indicates to the system that 16-bit memory access is
available.
I/O Chip Select 16
This output indicates to the system that 16-bit I/O access is available.
Refresh
"L" level input indicates that the system is refreshing its DRAM.
Memory Address
These outputs give the address of the display memory.
Row Address Strobe (RAS)
This output is the strobe signal for the row address latch.
Upper Column Address Strobe (UCAS)
This output is the strobe signal for the upper column address latch.
In the 2WE mode, however, it functions as the CAS signal.