MN66710 Datasheet, PDF (5/19 Pages) Panasonic Semiconductor – Full-Function DAB Receiver LSI

MN66710
I Pin Descriptions (continued)
Pin No. Pin Name I/O
Descriptions
Note
36
FW1
O General-purpose output window 1
Window for sub-channel 1 (audio)
37
FWFIC
O General-purpose output window 0
FIC window
38
FCLK3
O General-purpose data output clock 1.536 MHz continuous clock
39
FERF3
O General-purpose data output error flag Flag that indicates Viterbi-corrected bits
40
FDAT3
O General-purpose data output data
41
RAD4
O External DRAM address, bit 4
For connecting external DRAM
42
RAD5
O External DRAM address, bit 5
For connecting external DRAM
43
RAD6
O External DRAM address, bit 6
For connecting external DRAM
44
RAD3
O External DRAM address, bit 3
For connecting external DRAM
45
RAD2
O External DRAM address, bit 2
For connecting external DRAM
46
RAD1
O External DRAM address, bit 1
For connecting external DRAM
47
RAD0
O External DRAM address, bit 0
For connecting external DRAM
48
VSS2
 Digital system ground
49
VDD2
 Digital system power supply
50
RAD7
O External DRAM address, bit 7
For connecting external DRAM
51
RAD8
O External DRAM address, bit 8
For connecting external DRAM
52 NRAMOE
O External DRAM output enable
For connecting external DRAM
53
NRCAS
O External DRAM column address strobe For connecting external DRAM
54
RAD9
O External DRAM address, bit 9
For connecting external DRAM
55
NRRAS
O External DRAM row address strobe For connecting external DRAM
56 NRAMWE O External DRAM write enable
For connecting external DRAM
57
RDT1
I/O External DRAM data, bit 1
For connecting external DRAM
58
RDT0
I/O External DRAM data, bit 0
For connecting external DRAM
59
RDT2
I/O External DRAM data, bit 2
For connecting external DRAM
60
RDT3
I/O External DRAM data, bit 3
For connecting external DRAM
61
VSS3
 Digital system ground
62 DSPMON0 O DSP monitor, bit 0
Normally left open
63 DSPMON1 O DSP monitor, bit 1
Normally left open
64 DSPMON2 O DSP monitor, bit 2
Normally left open
65 DSPMON3 O DSP monitor, bit 3
Normally left open
66 DSPMON4 O DSP monitor, bit 4
Normally left open
67 DSPMON5 O DSP monitor, bit 5
Normally left open
68 DSPMON6 O DSP monitor, bit 6
Normally left open
69 DSPMNEN I DSP monitor output enable
A low level disables DSP monitor output
70
CIRSYN
O CIR display cycle signal
CIR monitor display trigger signal
71
CTLLR
O AFC/CIR D/A converter left/right clock For AFC control and CIR monitor display
72
CTLCLK
O AFC/CIR D/A converter clock
For AFC control and CIR monitor display
SDC00041BEM
5