MN66710 Datasheet, PDF (12/19 Pages) Panasonic Semiconductor – Full-Function DAB Receiver LSI

MN66710
I Electrical Characteristics (continued)
4. AC Characteristics at V_DD = 3.0 V to 3.6 V, V_REF5 = 4.75 V to 5.25 V, V_SS = 0.00 V, f_TEST = 24.576 MHz,
T_a = −30°C to +85°C (continued)
Parameter
Symbol
Conditions
Min Typ Max Unit
DRAM interface (continued)
Master clock/RAS delay time
t₁
Master clock/CAS delay time
t₂
Master clock/address delay time t₃
Master clock/WE delay time
t₄
Master clock/data input delay time t₅
Master clock/OE delay time
t₆
Data output setup time
t₇
Data output hold time
t₈
Audio interface
See figure 5.
7  32.5 ns
7  32.5 ns
27.5  57.5 ns
7  32.5 ns
27.5  57.5 ns
7  30 ns
0   ns
20   ns
SMCK clock period
SMCK high-level period
SMCK low-level period
SCLK period
SCLK high-level period
SCLK low-level period
SCLK delay time
SDAT delay time
SLRCK delay time
AUXDAT setup time
General-purpose data outputs
t_SMCK
t_SMCKH
t_SMCKL
t_SCLK
t_SCLKH
t_SCLKL
t_SCLKD
t_SDATD
t_SLRD
t_AUXS
See figure 6.
See figure 7.
72 81.38  ns
31   ns
31   ns
288 325.52  ns
100   ns
100   ns
  41 ns
  40 ns
  41 ns
8.5   ns
FCLK3 clock period
FCLK3 high-level period
FCLK3 low-level period
FCLK3 delay time
FDAT3 delay time
FERF3 delay time
FWFIC and FW1:4 delay time
t_FCLK
t_FCLKH
t_FCLKL
t_FCLKD
t_FDATD
t_FERFD
t_FWD
See figure 8.
576 651.04  ns
200   ns
200   ns
  15.5 ns
  21.5 ns
  21 ns
  18 ns
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SDC00041BEM