MN35503 Datasheet, PDF (5/9 Pages) Panasonic Semiconductor – D/A Converter for Digital Audio Equipment

For Audio Equipment
MN35503
Table 1-2. MN35503 Operating Modes
Mode Selection Pins
Pin States and Operating Modes
M1 Includes pull-up resistor
H
M2 Includes pull-up resistor
L
M3
L
H
L
MA
L
H
L
H
MDAT
MB
LHLHLHLH
MCLK
MC
RSBUP
MLAT
MD
RSBDN
L
H
MODE
4₀ 4₁ 4₂ 4₃ 5₀ 5₁ 5₂ 5₃
6₀
6₁
Serial mode
H
H
L
H
L H LH
RSBUP
RSBDN
7₀ 7₁ 7₂ 7₃
Input data form
Right-packed
I²S
Right-packed
Input word length (bits)
16
20
to 20
16 20
LRCK level for left channel data
L
H
L
H
*1
*1
*1
*1
XIN clock frequency (f_s)
384 576 384 576 384/576 256/384
512
See Table 3. See Table 3.
384/576 256/384
CKO output frequency (f_s) 384 STOP 384 STOP 384 576
512
See Table 3. See Table 3.
DE-EMP.(f_s=[kHz])
Output level
VANS oversampling (f_s)
Theoretical signal-to-noise
ratio
(dB)
– 48 44.1 32 – 44.1 –
See Table 3.
– 44.1 –
0.598 × AV_DD
0.448 × AV_DD
64
94 64
96
64/96
64/96
64
122 138 122 138 122/138 116/132
122
Note*1: During 576 f_s operation and 384 f_s operation in modes 2₁ or 6₁, the chip supports f_s clock speeds up to 32 kHz; for other
modes, it supports up to 48 kHz.