MN35503 Datasheet, PDF (3/9 Pages) Panasonic Semiconductor – D/A Converter for Digital Audio Equipment

For Audio Equipment
MN35503
Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
MA
DIN
LRCK
BCK
MB
DV_DD2
CKO
DV_SS2
M1
OUT1C
N.C.
AV_DD1
OUT1D
AV_SS1
AV_SS2
OUT2D
AV_DD2
N.C.
OUT2C
M2
DV_SS1
XOUT
XIN
DV_DD1
M3
MC
MD
PDO
Function Description
Operating mode selection pin 4
(See Table 1.)
Serial data input pin (MSB first)
LR synchronization signal input pin (f_s rate)
Data shift bit clock input pin
Operating mode selection pin 5
(See Table 1.)
Power supply pin 2 for digital circuits
Clock output pin
Ground pin 2 for digital circuits
Operating mode selection pin 1, with pull-up resistor
(See Table 1.)
PEM output pin 1C (Left channel with reversed phase)
No connection (Leave this pin open.)
Power supply pin 1 for analog circuits
PEM output pin 1D (Left channel with reversed phase)
Ground pin 1 for analog circuits
Ground pin 2 for analog circuits
PEM output pin 2D (Right channel with reversed phase)
Power supply pin 2 for analog circuits
No connection (Leave this pin open.)
PEM output pin 2C (Right channel with reversed phase)
Operating mode selection pin 2, with pull-up resistor
(See Table 1.)
Ground pin 1 for digital circuits (Ground for oscillator circuit)
Crystal oscillator pin
Crystal oscillator pin (external clock input pin) (Built-in feedback resistor)
Power supply pin 1 for digital circuits (for oscillation circuit)
Operating mode selection pin 3
(See Table 1.)
Reset pin/digital attenuation control pin
(See Table 1.)
Reset pin/digital attenuation control pin
(See Table 1.)
Phase comparator output pin (tristate output)*1
Note*1: This pin provides tristate output indicating the result of comparing the phases of the internal f_s-rate-signal and the
LRCK input signal. It is at "H" level when the LRCK signal leads and is at "L" level when the signal lags. At all other
times, it is in the high-impedance state.