MN101E51 Datasheet, PDF (5/10 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

MN101E51/52 Series
 Features (continued)
 Watchdog timer
Software processing error detection cycle is selectable from fs/2¹⁶, fs/2¹⁸, fs/2²⁰
System reset is generated by the hardware when software processing error is detected twice
 Watchdog timer2
Software processing error detection cycle is selectable from frcs/2⁴, frcs/2⁵, frcs/2⁶, frcs/2⁷, frcs/2⁸, frcs/2⁹, frcs/2¹⁰, frcs/2¹¹,
frcs/2¹², frcs/2¹³, frcs/2¹⁴, frcs/2¹⁵
System reset is generated by the hardware when software processing error is detected twice
 Buzzer output (MN101EF51A only)
Output frequency is selectable from fpll/2⁹, fpll/2¹⁰, fpll/2¹¹, fpll/2¹², fpll/2¹³, fpll/2¹⁴, fslow/2³, fslow/2⁴
 Remote control carrier output
Remote control carrier of 1/2 or 1/3 duty cycle can be output based on timer 0
 A/D converter
10-bit × 12 channels (MN101EF51A)
10-bit × 8 channels (MN101EF52A)
 Serial Interface:
3 systems
Serial 0 (Full duplex UART / Synchronous serial interface)
Synchronous serial interface
Transfer clock source: fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4, Timer 0 to 2,
Timer A output divided by 1, 2, 4, 8, 16, External clock
MSB/LSB can be selected as the first bit to be transferred, arbitrary size of 1 to 8 bits are selectable.
Continuous transmission, continuous reception, continuous transmission/reception are available.
Full duplex UART (Baud rate timer: selected from timer 0 to 2, or timer A)
Parity check, overrun error/framing error are detected
Transfer bits of 7 to 8 are selectable
Serial 1 (Full duplex UART / Synchronous serial interface) (MN101EF52A does not have this function)
Synchronous serial interface
Transfer clock source: fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4, Timer 0 to 2,
Timer A output divided by 1, 2, 4, 8, 16, External clock
MSB/LSB can be selected as the first bit to be transferred, arbitrary size of 1 to 8 bits are selectable.
Continuous transmission, continuous reception, continuous transmission/reception are available.
Full duplex UART (Baud rate timer: selected from timer 0 to 2, or timer A)
Parity check, overrun error/framing error are detected
Transfer bits of 7 to 8 are selectable
Serial 4 (Multi master IIC / Synchronous serial interface)
Synchronous serial interface
Transfer clock source: fpll-div/2, fpll-div/4, fpll-div/8, fpll-div/32, fs/2, fs/4, Timer 0 to 2,
Timer A output divided by 1, 2, 4, 8, 16, External clock
MSB/LSB can be selected as the first bit to be transferred, arbitrary size of 1 to 8 bits are selectable.
Continuous transmission, continuous reception, continuous transmission/reception are available.
Multi master IIC
7-bit slave address is settable
General call communication mode is supported
Ver. AEM
5