MN101E51 Datasheet, PDF (2/10 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

MN101E51/52 Series
 Features
 ROM capacity
32 KB
 RAM capacity
1 KB
 Package:
MN101EF51A
44-Pin QFP (10 mm × 10 mm / 0.8 mm pitch)
48-Pin TQFP (7 mm × 7 mm / 0.5 mm pitch)
MN101EF52A
32-Pin TQFP (7 mm × 7 mm / 0.8mm pitch)
 Machine Cycle:
High-speed mode
0.05 ms / 20 MHz (2.7 V to 5.5 V)
0.125 ms / 8 MHz (1.8 V to 5.5 V)
Low-speed mode
62.5 ms / 32 kHz (1.8 V to 5.5 V)
 Clock Gear Circuit:
Internal system clock speed is changeable by selecting division ratio of oscillation clock. (Divided by 1, 2, 4, 16, 32, 64, 128)
 High-speed Clock (fpll-div) Gear Circuit for peripheral functions:
Can be selected among "stop", fpll/1, fpll/2, fpll/4, fpll/8, and fpll/16.
 Oscillation Circuit: 4 types
High-speed (Internal oscillation: frc), High-speed (crystal/ceramic: fosc),
Low-speed (Internal oscillation: frcs), Low-speed (crystal/ceramic: fx)
High-speed internal oscillation 20 MHz / 16 MHz (selectable)
Low-speed internal oscillation 30 kHz
 Clock Multiplication Circuit:
PLL circuit output clock (fpll) fosc multiplied by 2, 3, 4, 5, 6, 8, 10, 1/2 × frc multiplied by 4, 5 enabled
* When clock multiplication circuit is not used, fpll = fosc or fpll = frc
 Operation Mode
NORMAL mode (high-speed mode)
PLL mode
SLOW mode (low-speed mode)
HALT mode
STOP mode
and operation clock switching
 Operating Voltage
1.8 V to 5.5 V
 Operating Ambient Temperature:
-40°C to +85°C
2
Ver. AEM