MN101E51 Datasheet, PDF (1/10 Pages) Panasonic Semiconductor – 8-bit Single-chip Microcontroller

MN101E51/52 Series
8-bit Single-chip Microcontroller
 Overview
The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C series) incorporate
multiple types of peripheral functions. This chip series is well suited for automotive power window, camera, VCR, MD,
TV, CD, LD, printer, telephone, home automation, pager, air conditioner, PPC, fax machine, music instrument and other
applications.
This LSI brings to embedded microcomputer applications flexible, optimized hardware configurations and a simple
efficient instruction set. MN101EF51A/52A has an internal 32 KB of ROM and 1 KB of RAM. Peripheral functions include
5 (MN101EF52A: 4) external interrupts, 20 (MN101EF52A: 18) internal interrupts including NMI, 8 timer counters, 3
(MN101EF52A: 2) types of serial interfaces, A/D converter, 2 types of watchdog timer and buzzer output (MN101EF52A: no
buzzer). The system configuration is suitable for system control microcontroller such as camera, timer selector for VCR, CD
player, or minicomponent.
With 5 oscillation systems (high-speed (internal frequency: 20 MHz), high-speed (crystal/ceramic frequency: max. 10 MHz)
/ low-speed (internal frequency: 30 kHz), low-speed (crystal/ceramic frequency: 32.768 kHz) and PLL: frequency multiplier of
high frequency) contained on the chip, the system clock can be switched to high-speed frequency input (NORMAL mode), PLL
input (PLL mode), or to low-speed frequency input (SLOW mode). The system clock is generated by dividing the oscillation
clock or PLL clock. The best operation clock for the system can be selected by switching its frequency ratio by programming.
High speed mode has the normal mode which is based on the clock dividing fpll, (fpll is generated by original oscillation and
PLL), by 2 (fpll/2), and the double speed mode which is based on the clock not dividing fpll.
A machine cycle (minimum instruction execution time) in the normal mode is 200 ns when the original oscillation fosc is
10 MHz (PLL is not used). A machine cycle in the double speed mode, in which the CPU operates on the same clock as the
external clock, is 100 ns when fosc is 10 MHz. A machine cycle in the PLL mode is 50 ns (maximum).
 Product Summary
This datasheet describes the following model.
Model
ROM Size
RAM Size
Classification
MN101EF51A
MN101EF52A
32 KB
1 KB
Flash EEPROM version
Note) DMOD internal pull-up resistor is in only Flash EEPROM version.
When using In-circuit Emulator, it is necessary to connect the pull-up resistor on the circuit board.
Package
QFP044-P-1010F
TQFP048-P-0707B
TQFP032-P-0707A
Publication date: March 2012
Ver. AEM
1