MN6155 Datasheet, PDF (4/9 Pages) Panasonic Semiconductor – PLL LSI with Built-In Prescaler

MN6155
For Communications Equipment
MN6155 Frequency Dividing Data Settings
1) Comparator side frequency dividing data
FV = F_IN ÷ {(16 × N) + A}
2) Reference side frequency dividing data
a)
b)
where
Low-speed operation (RSL pin at "H" level, using X_IN)
FR = X_IN ÷ R
High-speed operation (RSL pin at "L" level, using R_IN)
FR =R_IN ÷ {(16 × NR) + AR}
F_IN : Comparator side frequency
R_IN : High-speed reference frequency
X_IN : Low-speed reference oscillator frequency
FV : Comparator frequency divider stage output frequency
FR : Reference frequency divider stage output frequency
N : Setting for 14-bit programmable counter on comparator side
A : Setting for 4-bit swallow counter on comparator side
R : Setting for 17-bit programmable counter on low-speed reference side
NR : Setting for 13-bit programmable counter on high-speed reference side
AR : Setting for 4-bit swallow counter on low-speed reference side
(Note that N should be greater than A; NR, greater than AR.)
N-Side Latch Data
MSB
14 bits
Programmable
counter setting (N)
4 bits
LSB
Swallow counter
setting (A)
R-Side Latch Data
Low-speed operation
MSB
17 bits
LSB
Programmable counter
setting (N)
High-speed operation
MSB
13 bits
Programmable counter
setting (NR)
4 bits
LSB
Swallow counter
setting (AR)