MN6155 Datasheet, PDF (1/9 Pages) Panasonic Semiconductor – PLL LSI with Built-In Prescaler

For Communications Equipment
MN6155
PLL LSI with Built-In Prescaler
Overview
The MN6155 is a CMOS LSI for a phase-locked loop
(PLL) frequency synthesizer with serial data parameter
input.
It consists of a two-coefficient prescaler, variable
frequency divider, phase comparator, and charge pump.
It offers high-speed operation on a low power supply
voltage (1.0 to 1.4 V) and low power consumption (1.65
mW for V_DD=1.1 V, F_IN= R_IN=90 MHz).
Other features include intermittent operation by the
power save (PS) control signal and high-speed pull-in that
rapidly corrects the phase differences occurring at the start
of operation.
It also offers two choices for the reference signal: self-
excited operation using the built-in inverter amplifier or
use of an external, separately excited oscillator.
Features
Low power supply voltage: V_DD=1.0 to 1.4V
Low power consumption: 1.65mW(V_DD=1.10V,
F_IN=90MHz, R_IN=90MHz)
High-speed operation: F_IN=90MHz, R_IN=90MHz
(V_DD=1.1V)
Frequency dividing ratios in reference frequency
dividing stage
6 to 131,070 for RSL at "H" level
(even number setting is available)
272 to 131,071 for RSL at "L" level
Frequency dividing ratios for comparator stage: 272
to 262,143
Power supply pin for built-in charge pump
V_CP=2.5 to 3.2V
Output monitor pins for both comparator and reference
frequency dividing stages
Pin Assignment
X_IN
X_OUT
FV
V_DD
D_OP
V_SS
V_CP
F_IN
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
(TOP VIEW)
SSOP016-P-0225
R_IN
RSL
LC
FR
PS
LE
DATA
CLK